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Design >> Analog Design >> Simulation problem on the effect of decoupling cap
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Message started by taofeng on Aug 16^th, 2007, 2:52pm

Title: Simulation problem on the effect of decoupling cap
Post by taofeng on Aug 16^th, 2007, 2:52pm

Dear,

I am using the attached schematic to simulate the effect of Decoupling capacitor (someone may call it bypass , anyway it does not really matter) on the reduction of the power supply current transient as probably known to all of you guys.
However, no matter how I change the value of Decap (C2 in the schematic), the Current see from the power supply (V1) and the Current flowing through the inverter (Pmos transistor) remain exactly the same, which means that the C2 does not supply the transient . It seems really strange, I do not know what is wrong with this setup ?
Hope someone can give me some hint ! thanks

Jeffrey

Title: Re: Simulation problem on the effect of decoupling
Post by tosei on Aug 16^th, 2007, 5:26pm

Hi Jeffrey,

If you are referring to the transient current generated every time the inverter switches, then it is ok not to see any current being provided by the bypass cap. The reason is simple: the voltage across the cap is constant, and since the current through a cap is given by the rate of change (slope) of the voltage across it, then that current will always be 0.

Instead of using an ideal voltage source (which can provide transient currents as fast as you want) you could put a series resistor in between the voltage source and the cap. If the transient current is fast enough it will be the cap who is going to provide it.

Tosei.

Title: Re: Simulation problem on the effect of decoupling
Post by sheldon on Aug 17^th, 2007, 7:31pm

Jeffrey,

As Tosei, it is difficult to analyze the effect of bypassing when using ideal
supplies. Here are some additional points to consider, I'm others will have
other suggestions:
1) Isolate both the power supply and the ground from the circuit, using an
ideal ground may be a bigger issue than an ideal voltage source
2) Include the entire parasitic network in the analysis
a) board traces, consider frequency, is it okay to use an RLC model
or should they be modeled as transmission lines
b) Coupling between board traces, M and C
c) The package model should include R, L, C, and M (at least for adjacent
pins)
d) bond wires models as above
e) substrate contact: top-side [bond wire] or back-side [down bond]
3) design of the bypass network
Location of the bypass capacitor: on-chip or off-chip,

Title: Re: Simulation problem on the effect of decoupling
Post by sheldon on Aug 17^th, 2007, 7:38pm

Jeffery,

Sorry happy fingers:

3) Design of the bypass network
a) Location of the bypass capacitors: on-chip or off-chip
b) For off-chip capacitors, the type of capacitors used
different capacitors have different characteteritics, ESR, ESL, ...
c) For on-chip capacitors, use device models do not use ideal
capacitors, for example, a MOS gate capacitor value is bias
dependent

2) one other thing I forgot,
f) include the effect of the on-chip power supply routing

The list is fairly exhaustive and not all effects need to be included,
but, what needs to be included is design specific. You need to think
carefully about what you are trying to simulate and build a model for
the power supply distribution systems that accurately reflects the
implementation.

Best Regards,

Sheldon