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Design Languages >> Verilog-AMS >> passing parameters from verilog-a to ADE
https://designers-guide.org/forum/YaBB.pl?num=1187755711

Message started by dhruvaghai on Aug 21^st, 2007, 9:08pm

Title: passing parameters from verilog-a to ADE
Post by dhruvaghai on Aug 21^st, 2007, 9:08pm

Hi

I am working with a verilog-a code. I wish to be able to pass one of the parameters in that code to
ADE. Maybe I am supposed to create a paramter by that name in the CDF or something...
cannot find any suitable link that can help...if anyone knows please tell me...

Title: Re: passing parameters from verilog-a to ADE
Post by Geoffrey_Coram on Aug 23^rd, 2007, 6:03am

just started wrote on Aug 21^st, 2007, 9:08pm:

Pass a parameter from Verilog-A to ADE? That sounds backwards. Do you mean, you want to be able to set a parameter for an instance that is modeled with Verilog-A? Creating the CDF parameter would be a good start; I don't know if your netlister needs some changes, too.

Title: Re: passing parameters from verilog-a to ADE
Post by just started on Aug 23^rd, 2007, 8:08am

Actually I did get it...created a output voltage node in the code...passed the parameter to that node and passed that node to ADE...i wish to run monte carlo on that parameter...