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Design >> Analog Design >> CMFB of OTA
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Message started by min on Aug 22^nd, 2007, 1:40am

Title: CMFB of OTA
Post by min on Aug 22^nd, 2007, 1:40am

Hi all:
recently I simulate a fully differential OTA with cmfb , the circuit like the picture , I want to know is the cmfb design right? and I want to know that why not use the capacitor to sample the common mode of output?

I simulate the circuit in open loop, the load is 600fF capacitor, and the dc gain is so small. But in circuit , all the transistor is in saturation region , I don't know why , can anyone tell me , thanks

Title: Re: CMFB of OTA
Post by sheldon on Aug 22^nd, 2007, 2:34am

Min,

1) According to your schematic the common-mode level sensing
resistors are 1kOhm. This is low value, how much open loop
gain does your design have?

2) Controlling the common-mode level through the level sensing
resistors is unusual and it seems like this is not a very
efficient method.

3) Since you have provided any information on the how you are
using the op-amp, it is difficult to comment on whether using
a capacitor is appropriate or not. Is the application continuous-
time or discrete-time time, that is, switched capacitor. It is
easier to use a capacitor in switching circuits than continuous
time circuits.

Best Regards,

Sheldon

Title: Re: CMFB of OTA
Post by tosei on Aug 22^nd, 2007, 2:12pm

Hi,

In addition to Sheldon comments, I'd like to add the following:

- The input of your CMFB circuit is tied to the middle point of the sensing resistors and also to the drain of the NMOS active load (at the right). This is not good since you are heavily reducing the common mode gain of your circuit (by reducing the impedance at that node) and also unbalancing such circuit, since the current that should flow through the active load is the one comming from Vbias current source / 2. Finally, your differential circuit would be heavily loaded (on top of the 1K sensing resistors load, which I agree sound like too small), may be too much for what is intended to drive (may be this is the reason why you are getting too small dc gain).

- I cannot see in your schematic where the CM feedback signal is applied! If you are trying to control the output CM level by just forcing the connection of the middle point I mentioned above, I do not think that will work and actually it would not be a CM FEEDBACK circuit. What it is usually done in this case is generate Vbias4 from the gate voltage of the CMFB active load, assuming the correct sizing and current levels for these devices.

Regards
Tosei