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Design Languages >> Verilog-AMS >> Test bench design - tasks
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Message started by jjrael on Aug 24^th, 2007, 10:09am

Title: Test bench design - tasks
Post by jjrael on Aug 24^th, 2007, 10:09am

All,

I am starting to write verilogAMS test benches to verify the functionality of my schematics and models. I want to reuse my code so I am trying to fold them into a task. However, I am running into problems when I try to pass a analog signal to the task. For example I have a task call e_20MHz and I pass it an "analog" port:

e_20MHz(I0.X1);

My task is define:

task e_20MHz;
input in1;
real in1;

real tp0;
real tp1;
real tp_val;
begin
tp0 = V(in1);
#25 tp1 = V(in1);
tp_val = (tp0 - tp1)/2.0;
$fdisplay(d_fd,"%7.3f\tE@20MHz XO\t%5.2g", $abstime*1e6, tp_val);
end
endtask // e_20MHz

When I run, I get this error:

verilog.vams
tp0 = V(in1);
|
ncvlog: *E,EXPBON (/xxx/verilog.vams,87|19): Expecting only branch or node type arguments [5.2(AMSLRM)].
#25 tp1 = V(in1);
|
ncvlog: *E,EXPBON (/xxx/verilog.vams,88|23): Expecting only branch or node type arguments [5.2(AMSLRM)].
module xxx.v_XO2:verilogams
errors: 2, warnings: 0

Any ideas?

Title: Re: Test bench design - tasks
Post by Mighty Mouse on Aug 24^th, 2007, 10:57am

Have you tried declaring in1 as being electrical? That seems to be what is missing.

-MM

Title: Re: Test bench design - tasks
Post by jjrael on Aug 24^th, 2007, 11:04am

ncvlog did not like that at all:

electrical in1;
|
ncvlog: *E,MISEXX (/xxx/verilog.vams,80|19): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].

jr

Title: Re: Test bench design - tasks
Post by Geoffrey_Coram on Aug 27^th, 2007, 5:20am

Are you `including discipline.vams (or .h) to get the definition of electrical?

Also, I'm thinking that V() isn't allowed in tasks (I know it's not allowed in functions). You need a module with an electrical port, and then have a real variable Vin1 = V(in1) that gets passed to the task. In any case, you shouldn't have real and electrical applied to the same input.