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Design >> Analog Design >> Req. Reference: +/-1% accurate On-Chip Oscillator
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Message started by packiaraj on Aug 27^th, 2007, 1:55am

Title: Req. Reference: +/-1% accurate On-Chip Oscillator
Post by packiaraj on Aug 27^th, 2007, 1:55am

Hi,
We need accurate on-chip oscillator for "charge measurement". The frequency of oscillator is ~2MHz. But the frequency variation over PVT should be limited to +/- 1%. :o
Is it possible to realize such an on-chip oscillator? ::) Any material / reference / previous work in thesis form would be really appreciated. 8-)
Note: Use of Crystal is not allowed due to pin-count reason.
Process: 0.35um; Supply Current: 50 uA. Trimming is allowed [Obviously the no. of trim bits is limited.]

Thanks,
Packiaraj.V.

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by Visjnoe on Aug 27^th, 2007, 11:18am

Dear,

such an accurate low-frequency oscillator can be constructed.

You could adopt the so-called RC-oscillator topology and counteract PVT variations as follows:

1. Use a trimmable capacitor bank to counteract the effect of process variations (on the frequency)
2. Use a combined resistor with cancelling positive/negative temperature coefficients to counteract the effect of temperature variations (on the frequency)
3. Use an LDO to counteract voltage variations (most likely that even without the LDO you are within the 1% accuracy after steps 1 and 2)

Regards

Peter

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by packiaraj on Aug 27^th, 2007, 10:44pm

Thanks for your suggestions, Peter. :-?
Does the +Ve/-Ve Temp coefficients of "R" cancel perfectly that we don't need Trimming [To counter-act R variation over Temperature] to achieve +/1% accuracy? [Though How Trimming for Temperature variations is done is a question :( ]. This +/-1% accuracy should be met over 6-sigma [Process and Mismatch variation]. [The Stigma of Six-Sigma :P]

Please see the Doc. attached for Figure taken from "A Temperature Compensated Fully Trimmable On-Chip IC Oscillator" by A. Olmos. The idea is similar.
i.e., Combine IPTAT+ICTAT=IREF and use Trimming to control IREF Vs Temp variations. And use only C [No Trmming for C , As It would call for huge area.]. Let the Temp Trimmed Current be IREF_T.
However the on-chip variation of C is counter-acted by changing the current "IREF_T" using another magnitude trimming. Let this current be IREF_TM

dV/dt=IREF_TM/C
1/dt=IREF_TM/[C*dV]=2*Frequency

Here dV is the Trimmed BandGap Voltage used for comparing the voltage across a Capacitor. This Capacitor is charged and discharged using IREF_TM during the alternate phases.
But, as you could see, this involves 2 levels of Trimming. I am curious to know If there would be a better method to realize Low-Frequency, Highly accurate OSC? [Better architecture with not-so-much of Trimming]

Thanks,
Packiaraj.V.

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by packiaraj on Aug 27^th, 2007, 11:13pm

Sorry, I could not attach the Image. I give here the IEEE Xplore link of the Paper:

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1232826

Thanks,
Packiaraj.V.

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by MonteCarlo on Sep 1^st, 2007, 3:40am

Packiaraj.V,

I would use the 2 stage trimming that you suggest because your spec is so extreme. Just beware that with such a high level of accuracy you are subject to other errors such as:

package shift
measurment error

To avoid package shift, you should use a post-package trim method.
MonteCarlo

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by packiaraj on Sep 3^rd, 2007, 12:33am

Thanks for your suggestions MonteCarlo.
BTW, Can you site reference(s) to "Post Package Trim" ?

Thanks,
Packiaraj.V.

Title: Re: Req. Reference: +/-1% accurate On-Chip Oscilla
Post by MonteCarlo on Sep 3^rd, 2007, 3:29pm

No references I'm sorry.

What I mean by post-package is that you can program the trim after packaging. Some trim technologies are more suited to programing at wafer level.

-Monte