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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> initial_step for dc sweep https://designers-guide.org/forum/YaBB.pl?num=1188397763 Message started by dilbert on Aug 29th, 2007, 7:29am |
Title: initial_step for dc sweep Post by dilbert on Aug 29th, 2007, 7:29am Somehow the "initial_step" block doesn't work for dc sweeps (i'm using cadence 5.10.41). The block is executed and the values are set correctly, but in the following steps of the sweep all variables are set to zero. (See the example below) What can I do? Thanks! Code:
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Title: Re: initial_step for dc sweep Post by Geoffrey_Coram on Aug 31st, 2007, 8:13am You should probably upgrade your version of Spectre. Back at the time that 5.10.41 was released, there was still some confusion in the Verilog-AMS LRM as to what "initial_step" should do for a dc sweep, since "initial_step" was originally intended for transient analyses. LRM2.2 specifies when initial_step should be true for various points of various spice-like analyses. |
Title: Re: initial_step for dc sweep Post by tdlrali on Jul 2nd, 2014, 4:38am Sorry for unburying this old thread, but I have this exact issue. I'm trying to simulate the static behavior of a DAC with a DC analysis, using an ideal ADC to provide the digital input for the DAC. I'm using the following VerilogA ADC (from the Verilog-A examples on this site): Code:
In an DC analysis, the output of the ADC is all low, no matter what the input voltage is. By adding a $debug output, I can see that the analog section/initial_step is only run once (with in=0V), but not for each subsequent DC operating point. I'm using Cadence/Spectre to simulate. How can I force Spectre to run the analog section / trigger the initial_step for each step? Spectre Version: 12.1.1.164.isr15 |
Title: Re: initial_step for dc sweep Post by Geoffrey_Coram on Jul 8th, 2014, 7:46am Have you tried using the "above" event? The description says it is supposed to trigger in dc, unlike cross. |
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