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Design Languages >> Verilog-AMS >> Syntax error while using genvar
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Message started by magathi on Aug 31^st, 2007, 10:30am

Title: Syntax error while using genvar
Post by magathi on Aug 31^st, 2007, 10:30am

Iam just tring to implement the adc example in the 'designers guide to verilog ams'
This is part of the code Iam using....

parameter integer bits = 8 from [1:24];
genvar i;
integer g;

analog begin
@(cross(V(clk)-thresh,+1) or initial_step) begin
sample =V(in);
midpoint = fullscale/2.0;
for (g=bits-1; g>=0; g=g-1)begin
if (sample>midpoint) begin
result[g]=vdd;
sample = sample-midpoint;
end
else begin
result[g]=0.0;
end
sample =2.0*sample;
end
end //end cross

for (i=0;i<bits; i= i+1)
begin
V(out[i])<+transition(result[i],td,tt);
end
end //analog end

when I try simulating this using AMS (Analog design environment XL) this is the error I get....
Error found by spectre.
Problem found in instance `pip_adc_top.I9' of module `pip_adc'
for (i=0;i<bits; i= i+1)
|
ncelab: *E,SYERROR (/home/mjayara/test/pip_adc_top/adexl/results/data/Interactive.44/1/test:pip_adc_top:1/netlist/ihnl/test/pip_adc/verilogams/verilog.vams,39|11): In for-loop control, genvar expression can only consists of integer constant or other unrolled genvar variables expression.

Could someone help me out.... As far as I see it Iam using integer constants in the genvar expression......

Title: Re: Syntax error while using genvar
Post by Marq Kole on Sep 26^th, 2007, 1:49am

Hi,

Is the analog for-loop allowed to depend on a parameter in the version of AMS Designer you are using? You could try to replace the "bits" in the for-loop control by an integer constant. Is the "out" array terminal also dependent on "bits"? If not, try to use the same value here. In the past I've used macro variables to get around this limitation in Verilog-A/AMS compilers, i.e. `BITS.

Marq