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Design >> Analog Design >> Noise in PWM signals
https://designers-guide.org/forum/YaBB.pl?num=1188941785

Message started by tosei on Sep 4^th, 2007, 2:36pm

Title: Noise in PWM signals
Post by tosei on Sep 4^th, 2007, 2:36pm

Hi all,

One well known way to generate a PWM signal is to compare it to a ramp of a certain desired frequency. When the ramp crosses the threshold set by the signal the output waveform changes its state. Let's assume the signal is noiseless and all the noise is being generated in the ramp. If we also assume the ramp is simply generated by integrating a DC voltage reference, and disregarding any flicker noise associated to the circuit (just considering white noise sources), then the noise content of the ramp would be that of an integrated (in time) white noise. The resulting PSD would behave as 1/f^2. Since this noise has a larger power (integral over frequency) as lower frequencies are considered, then the question is:

Is the duty cycle (or phase) noise of the resulting PWM waveform increased due to the longer integrating time, if a lower PWM carrier frequency is generated? I see the noise power in volts increases on the generated ramp but how that is translated into DC noise in a longer time (lower carrier frequency). Is there any compensation effect?

Thanks in advance.
Tosei