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Design >> RF Design >> PLL Phase margin
https://designers-guide.org/forum/YaBB.pl?num=1189084019

Message started by analog_cha on Sep 6^th, 2007, 6:06am

Title: PLL Phase margin
Post by analog_cha on Sep 6^th, 2007, 6:06am

Hi
Is the PLL phase margin related to phase margin of the loop filter??
if so how it can be related??
If any one has good docs on pll stability, pls share with me..

Thanks.

Title: Re: PLL Phase margin
Post by Jess Chen on Sep 6^th, 2007, 8:14am

How is the phase margin of the loop filter defined?

Title: Re: PLL Phase margin
Post by analog_cha on Sep 6^th, 2007, 9:55pm

Let me explain my problem here.
The divider of my PLL is programmable. say 4 to 256. I designed the loop filter taking the divider value 32, a particular charge pump current and a phase margin of 55deg.
To meet the stability of the PLL for all the divider values, i assumed some values of the charge pump currents, say 4 currents.
Now, if i want to check the phase margin of the PLL for the other divider values and charge pump currents how to proceed??
Should i simulate PLL in the behavioral model or there is some other way??

Thanks.

Title: Re: PLL Phase margin
Post by Jess Chen on Sep 6^th, 2007, 10:11pm

I think you are asking about how charge pump current and divider ratio affect the loop gain. Both are simple gain elements in the overall loop gain. If you want to maintain a particular phase margin when you change the divider ratio by say a factor of 2, you have to change the charge pump current in the opposite direction by a factor of 2. The phase margin will remain unchanged but the phase noise may not, depending on where the dominant noise contributors lie.

If you want to simulate the phase margin for different parameters, you can write behavioral models in VerilogA or VHDLAMS and use Spectre, SPICE, ELDO, etc. If you prefer an analytic approach you use Matlab, Excel, Mathematica, etc. Either way you will need to use a phase domain model. Any half way decent book on PLLs will show you how to create the phase domain model and compute the loop gain and phase margin. Ideally you would do both and make sure the results agree.

Title: Re: PLL Phase margin
Post by analog_cha on Sep 6^th, 2007, 10:32pm

Thank you Jess.
But for a large range of divider values, i should use large range of charge pump currents to meet steady-phase noise perforamnce. Its very cumbersome.
Any way, i am not supposed (as per the requirement) to use many currents for my charge pump.
I used Excel and simulink to model the PLL. I have to re do it for different CP currents and divider ratios to find the Phase margin.