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Design Languages >> Verilog-AMS >> verilog-A time delay model
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Message started by dkumar on Sep 6^th, 2007, 6:09am

Title: verilog-A time delay model
Post by dkumar on Sep 6^th, 2007, 6:09am

Respected,
I have been looking for a time delay model where in i may also speed up the signal i.e can have a functionality of Z of z-transform in time domain.

I could only fine all the models where positive time delays can be done and not negative.

Can someone please help me with

Title: Re: verilog-A time delay model
Post by Jess Chen on Sep 6^th, 2007, 8:22am

I don't think your request is feasible because the world is causal. You can't observe a response before it happens. If one could, one could make a fortune in the stock market :)

The only way you can give a signal a negative delay is to give all other signals a positive delay.