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Design >> Analog Design >> high speed TTL output with rigorous load problem
https://designers-guide.org/forum/YaBB.pl?num=1189646829

Message started by Robert on Sep 12^th, 2007, 6:27pm

Title: high speed TTL output with rigorous load problem
Post by Robert on Sep 12^th, 2007, 6:27pm

hi, guys,
here i wanna design a TTL output interface circuit, the requirement is shown as following:

1. low logic level <500mV, high logic level = Vcc (offered by the external supply, independent on the chip supply)
2. the load is consisted of a 7.5Kohm pull up resistor parallel with a 20p capacitor.
3. the singal frequency is as higher as 100MHz.

i have been tried many prototypes, such as open drain、push pull、cherry hooper amplifier, however, non of them can reach the requirements. do you guys have any other structures or techniques、solutions, please post it, i really need your kindly help, thanks in advance.

best regards
Nio Lin

Title: Re: high speed TTL output with rigorous load probl
Post by ywguo on Sep 12^th, 2007, 7:50pm

Hi Nio,

Did you define the minimum value of high logic level? Any which spec does your TTL output violates?

Thanks
Yawei

Title: Re: high speed TTL output with rigorous load probl
Post by Robert on Sep 12^th, 2007, 8:33pm

hi, Yawei,
thanks for your reply, the output high logic level is not exactly required to equal to VCC(external), but we still expect it is not less than Vcc-0.3V.

Best Regards
Nio Lin

Title: Re: high speed TTL output with rigorous load probl
Post by Robert on Sep 13^th, 2007, 12:45am

Dear Yawei,
here the specification of Vcc (external) is in a range of 1.8V to 5.5V.

B.R.
Nio Lin

Title: Re: high speed TTL output with rigorous load probl
Post by ywguo on Sep 17^th, 2007, 1:38am

Hi Nio,

So Vcc-0.3V is your requirement for the minimum high output voltage. Don't you meet this spec, assume you have pull-up resistor?

Yawei