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Design Languages >> Verilog-AMS >> delay model in verilog-a (ac response)
https://designers-guide.org/forum/YaBB.pl?num=1189672310

Message started by cane-an on Sep 13^th, 2007, 1:31am

Title: delay model in verilog-a (ac response)
Post by cane-an on Sep 13^th, 2007, 1:31am

Hello,
The verilog-a manual says that the delay model in an ac simulation has a response of e(-jwt). This does not seem to be the case. I ran the code fragment:
V(out)<+absdelay(V(vin), const_t)
in ac and got a very large attenuation and 0 phase shift at all frequencies. Am I doing something wrong? Is there a way to model delays in ac?

Title: Re: delay model in verilog-a (ac response)
Post by Geoffrey_Coram on Sep 13^th, 2007, 4:25am

Are you sure you hooked everything up correctly -- does it work in transient, if you apply a sine input?

You have V(out) and V(vin) -- should it be V(vout) or V(in)? It could be that your "attenuation" is actually leakage due to GMIN and the delay isn't actually hooked up in the signal path.

Or it could be a simulator bug.