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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Varactor simulation https://designers-guide.org/forum/YaBB.pl?num=1189775907 Message started by Visjnoe on Sep 14th, 2007, 6:18am |
Title: Varactor simulation Post by Visjnoe on Sep 14th, 2007, 6:18am Dear all, I have a simulation set-up problem when it comes to simulating a varactor (actually 2) of which I want to determine the capacitance versus the tune voltage using following SPICE setup: Code:
The problem is that the Vtune source acts as a short to ground during an AC analysis. Therefore, my setup returns the effective capacitance C of 1 varactor instead of the correct C/2. I can solve this problem by inserting a 1GOhm resistor between the vtune source and the controlling node of the varactors. I was wondering if there is another approach to tackle this (setup) problem? Kind Regards Peter |
Title: Re: Varactor simulation Post by monte78 on Sep 14th, 2007, 8:51am Visjnoe wrote on Sep 14th, 2007, 6:18am:
Hello Peter, I think a better solution to bias a generic circuit and to exclude this effect in in the ac analysis is to put a large inductance instead of the 1GOhm resistance (1T Henry for example...). By this way the dc bias will be correct while during ac analysis the inductor can be considered as an open circuit. Bye Monte |
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