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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> SpectraVerilog sim: Glitch on AD/DA interface https://designers-guide.org/forum/YaBB.pl?num=1189776036 Message started by neoflash on Sep 14th, 2007, 6:20am |
Title: SpectraVerilog sim: Glitch on AD/DA interface Post by neoflash on Sep 14th, 2007, 6:20am Hi, folks: I do have a trouble with simulation with Spectra_Verilog. The problem is that there is often a lot of glitches on the interface signals between analog and digital. If the signal is a clock, it will incur double trigger. How to entirely solve this problem? Regards |
Title: Re: SpectraVerilog sim: Glitch on AD/DA interface Post by sheldon on Sep 16th, 2007, 9:29am Neo_Flash, It might be good to talk to your support AE. Questions and comments: 1) Which version of Spectre are you using? In more recent versions of Spectre should have better accuracy 2) What errpreset are you using? If you are doing something that requires a lot of accuracy, for example, simulation of an analog/digital feedback loop, then tighter accuracy control may help. In the past, using the Spectre transient option relref=pointlocal helped me for one tough circuit 3) Try AMS Designer if you have access to it Best Regards, Sheldon |
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