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Design >> High-Speed I/O Design >> Q on dual-edge triggered register&NSFF
https://designers-guide.org/forum/YaBB.pl?num=1189827797

Message started by scbeginner on Sep 14^th, 2007, 8:43pm

Title: Q on dual-edge triggered register&NSFF
Post by scbeginner on Sep 14^th, 2007, 8:43pm

hi all, i am a student in electronics. This semester i have two assignment questions where i do not have any clue to solve it. Try to put the questions here and hope can get some guides from you
question 1: a) sketch a dual-edge triggered register designed using static Master-slave latches 2) sketch a dual-edge triggered register designed using C2MOS register
question 2: design a cmos D FF with negative setup time (NSFF)