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Design Languages >> Verilog-AMS >> question about integral
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Message started by James Bond on Sep 15^th, 2007, 7:57am

Title: question about integral
Post by James Bond on Sep 15^th, 2007, 7:57am

Hi, all

I need some hint on how to write an integral model ?

module Integral(Vin,Vout);

output Vout;
input Vin;

analog begin

Vout <+ idt(Vin);

end

endmodule

Can you tell me the problem of this model?

Title: Re: question about integral
Post by James Bond on Sep 15^th, 2007, 8:13am

Hi,
I tried this, but the output is 0, what's the reason?
module Integral(in,out);

output out;
input in;
electrical in, out;
analog begin

V(out) <+ idt(V(in),0);

end

endmodule

Title: Re: question about integral
Post by Geoffrey_Coram on Sep 17^th, 2007, 5:26am

Looks OK to me -- can you post the netlist? Can't tell from the model if
a) V(in) is zero, so of course V(out) will be zero
b) V(out) is connected badly
c) you're running a dc analysis, where idt() gives 0

Title: Re: question about integral
Post by James Bond on Sep 17^th, 2007, 10:41am

Hi,

I have an ideal square wave input, Vpulse is from analoglib, it has V(in) from 0 to 200mV, frequency is 1GHz, the input is connected to the 'in'. The output is open circuit. I ran the transient simulation.

Could you tell me where might be the problem ? Thank you very much.

James

Title: Re: question about integral
Post by Geoffrey_Coram on Sep 17^th, 2007, 10:51am

It works for me.

I remember one simulator I used in the past used to round small voltages (< nV) to zero. Could this be happening to you? Try setting a larger input pulse voltage and changing the frequency to 1kHz (period to 1m).

Title: Re: question about integral
Post by James Bond on Sep 17^th, 2007, 10:56am

Hi,

I made a mistake, it's working now. I set the input voltage wrongly. Thank you for the hint.

Title: Re: question about integral
Post by James Bond on Sep 17^th, 2007, 11:55am

Hi,

I have a triangle output with dc 125mV, how can I reduce the dc voltage to 0V? I tried V(out)<+ idt(V(in),-0.125);,
But it doesn't work. Could you please tell me how can I do this ?

Thank you very much.

James

Title: Re: question about integral
Post by Geoffrey_Coram on Sep 18^th, 2007, 12:31pm

What do you mean, "it doesn't work" -- does the output start at -0.125 like it should?

When you say "triangle" do you mean a ramp? Surely not a sawtooth -- if you're still using the square-wave pulse, you should get a ramp while the pulse is high and a flat output when the pulse source is at zero.

Title: Re: question about integral
Post by James Bond on Sep 19^th, 2007, 1:33pm

Hi,

I am sorry for the confusing. Please have a look at the picture. The following is my code:

module Integral(in,out);

output out;
input in;
electrical in,out;

analog begin

V(out)<+1000000000* idt(V(in), 0);

end

endmodule

How can I reduce dc level of the triangle wave to make it be modulated by sinusoid signal?

Title: Re: question about integral
Post by Geoffrey_Coram on Sep 24^th, 2007, 7:51am

I'm confused: which is the input, and which the output?

I thought the output was the rapidly-varying wave, because you want a 0V dc level, which the slow sine wave has.

But earlier you were saying the input was Vpulse. I can't really tell the shape of the rapidly-varying wave.

The integral operator should not be producing a waveform that varies more rapidly than the input, unless you've got serious problems with numerical noise...

Title: Re: question about integral
Post by James Bond on Sep 24^th, 2007, 12:28pm

Hi,

It was my fault. I should have explained this before.

The triangle wave in the pic above is generated by integrating the ideal vpulse from analoglib. The sinusoid signal is another signal generated by another block, I don't have problem with this. Now I want to use this sinusoid signal to modulate the triangle wave and send them to the comparator. So the output of the comparator should be the modulated square wave (PWM).

Here you can clearly see that the sinusoid singal and triangle signal are not in the same level, the triangle wave can not be fully modulated. I want to modify the veriloga code of the integrator and move triangle wave down to sinusoid level , so it can be modulated. Could you please give me some suggestions ?

Best Regards
James

Title: Re: question about integral
Post by Geoffrey_Coram on Sep 25^th, 2007, 4:16am

If you set the vpulse to toggle between -100 and +100 mV, this should fix the dc level.

For the modulation, you could put an ideal multiplier in the module:

Code:

module mymod(pulse_in, sine_in, out);
inout pulse_in, sine_in, out;
electrical pulse_in, sine_in, out;
parameter real gain = 1000000000;
analog begin
V(out)<+ V(sine_in) * gain * idt(V(pulse_in), 0);
end
endmodule