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Design Languages >> Verilog-AMS >> accuracy of absdelay()
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Message started by Aigneryu on Sep 16^th, 2007, 9:42pm

Title: accuracy of absdelay()
Post by Aigneryu on Sep 16^th, 2007, 9:42pm

Hi,

Previous I used this model to model the finite delay in tri-state PFD.

module pfd_cp_ena_j (out, ref, vco, ena);

output out; electrical out; // current output
input ref; voltage ref; // positive input (edge triggered)
input vco; voltage vco; // inverting input (edge triggered)
input ena; voltage ena; // PFD enable control
parameter real ip=100u; // maximum sourcing current
parameter real in=100u; // sinking current
parameter real vh=+1; // input voltage in high state
parameter real vl=-1; // input voltage in low state
parameter real vth1=(vh+vl)/2; // threshold voltage at input
parameter real vth2=(vh+vl)/2; // threshold voltage for ena
parameter integer dir=1 from [-1:1] exclude 0;
// dir=1 for positive edge trigger
// dir=-1 for negative edge trigger
parameter real tt=1p; // transition time of output signal
parameter real td=0; // average delay from input to output
parameter real jitter=0; // white edge-to-edge jitter
parameter real ttol=1f; // time tolerance, recommend ttol << jitter
parameter real tidle=1n; // feedback delay in tri-state PFD

integer state_ref, state_vco, seed;
real dt;
real rst;

analog begin
@(initial_step)
begin
seed = 716;
rst=0;
end

@(cross((V(ref)-vth1), dir, ttol) or above(vth2-(V(ena)), ttol))
begin
if (V(ena) < vth2)
begin
state_ref = 0;
dt = jitter*$rdist_normal(seed,0,1);
end
else
begin
if (state_ref==0) state_ref = 1;
dt = jitter*$rdist_normal(seed,0,1);
end
end

@(cross((V(vco)-vth1), dir, ttol) or above(vth2-(V(ena)), ttol))
begin
if (V(ena) < vth2)
begin
state_vco=0;
dt = jitter*$rdist_normal(seed,0,1);
end
else
begin
if (state_vco ==0) state_vco = 1;
dt = jitter*$rdist_normal(seed,0,1);
end
end

@(above((rst-0.5), ttol))
begin
state_ref = 0;
state_vco = 0;
dt = jitter*$rdist_normal(seed,0,1);
end

// rst=idtmod(2/tidle*state_ref*state_vco, 0, 1, -0.5);
rst=absdelay((state_ref&&state_vco), tidle);
I(out) <+ transition(-ip*state_ref+in*state_vco, td+dt , tt);
// I(out) <+ transition(iout*state, td + dt, tt);

end
endmodule

However, I found it is very critical to simulate the feedback delay correctly with time step control of transient simulation.
With tidle=1n, and run transient directly, the delay will become 1.xns.
If I tighten the maxstep, the delay will approach to 1ns. I thought verilog-A should be able to capture the delay correctly since it is event-driven simulator. And I just do not want to set to tight limits on the maxstep for the sake of speed. Does anybody have any good suggestion?

Title: Re: accuracy of absdelay()
Post by Ken Kundert on Sep 16^th, 2007, 11:28pm

Verilog-A is not event-driven.

How are you observing the delay from absdelay? I don't see where the output is ever used.

Why do you specify delay both with the transition and the absdelay? Absdelay is a heavy function that is designed to analog signals. Since you are passing piecewise constant signals, you would be better served using the delay in the transition function.

-Ken

Title: Re: accuracy of absdelay()
Post by Aigneryu on Sep 17^th, 2007, 10:13am

Hi,

I use absdelay() to model the finite delay time of the tri-state PFD, the delay is usually made longer on purpose to deal with the deadzone problem caused by slow turn-on time of the chargepump. So I need this feedback reset to have much longer delay than td, which should be the dealy from digital state to current output. In sum, I need a delay when current is on, but different delay when the current is off. Is there a more sophisticated way to do this?

Sincerely,