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Design >> RF Design >> layout unused area
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Message started by aaron_do on Sep 17^th, 2007, 12:58am

Title: layout unused area
Post by aaron_do on Sep 17^th, 2007, 12:58am

Hi all,

for the unused area in the layout, i was thinking i should add metal with contacts to substrate. This would be to improve the grounding of devices and reduce substrate noise. Is this good practice, or is there a problem?

thanks,
Aaron

Title: Re: layout unused area
Post by ACWWong on Sep 17^th, 2007, 5:09am

How are you expecting to connect the metal of the "metal with contacts to substrate" ?

if left floating (with only the resitive connection to sub) i can't see how you would be improving the grounding of devices and reducing substrate noise ??

if metal star connected back to appropriate ground pad then this is usual method for substrate ring protection.

For unused layout area, you need to identify what "unused" really is... typically it'll be pwell (not p sub), so will connect adjacent P+ substrate connects with finite impedance. If this is unwanted (i.e. between two circuits with their own sub rings which you want to isolate), then its a good idea to put things inbetween, such as n layer (or trench if you have it) or at least spare dummy devices.

Title: Re: layout unused area
Post by aaron_do on Sep 17^th, 2007, 7:07am

Hi,

sorry for the confusion. The technology i'm using is psub with nwell (no pwells). For most of my circuits, i've tried to maintain a symmetric differential layout. As such, there's quite a bit of unused area. Basically i mean to fill it up with guard ring which is all connected back to the ground pad. By filling up unused areas, i hope to reduce the substrate resistance over those particular areas. So you're saying this is the normal thing to do right? I didn't really get the part about adding the spare dummy devices...could you elaborate?

thanks,
Aaron

Title: Re: layout unused area
Post by cmc on Sep 17^th, 2007, 1:48pm

Besides fixing the substrate, consider using unused space for decoupling caps for noise sensitive nodes, power rails etc.. You can never have enough decoupling.

Title: Re: layout unused area
Post by Berti on Sep 17^th, 2007, 10:26pm

Hi Aaron,

I agree with cmc's advise. I would fill this area with bypass capacitors. This helps
to reduce ringing on the supply and filters supply noise. I don't think that you gain
much when filling the area with pwell-contacts, since you probably won't have a
seperate ground pad only for this purpuse. And a guard-ring is only effective
when it is connected to a quiet sepereted ground. Furthermore, making the substrate
low-resistive even favors coupling paths. I think low-resistive substrate conntacts are
only usefull when they are close to your devices.
But nevertheless, add enough substrate-contacts to the bypass caps to prevent latch-up.

Cheers

Title: Re: layout unused area
Post by carlgrace on Sep 19^th, 2007, 6:37am

I agree with Berti and cmc with one caveat: be careful of resonance between your coupling cap and the bondwire and board inductances you expect. The resonance frequency of the bondwire and the coupling caps is proportional to the square root of the coupling capacitance, so a 4X increase in coupling cap reduces the resonance frequency by 2X. Be careful that this frequency is well above your operating frequency, and try to do a simulation including the expected parasitic inductance in your circuit.

If you have trouble, one idea is to put a small resistor in the series with your coupling cap. This will kill the Q of the capacitors with the tradeoff being it is not as good as a bypass device.

Good luck,
Carl

Title: Re: layout unused area
Post by aaron_do on Sep 19^th, 2007, 7:40am

Hi all,

thanks for all the replies. I expect that i'm gonna end up with somewhere in the tens of picofarads of supply coupling caps. And the bondwire is likely in the 0.1 nH range. With an operating frequency of 2.4 GHz i think i can be fairly certain that the resonant frequency of the supply bondwires with the coupling caps will be less than 2.4 GHz. So you're saying that this will be a problem? Just want to make sure,

thanks,
Aaron

Title: Re: layout unused area
Post by carlgrace on Sep 19^th, 2007, 1:26pm

Aaron,

A couple of comments. First, if you have 20pF of bypass cap along with 0.1 nH of inductance that will resonate at 3.6 GHz. I am extremely dubious that you have 0.1 nH of bondwire inductance. A bondwire in a typical package is about 1.5 nH, a downbond if you are using a paddle for your system ground is about 0.5 nH. The efficacy of putting downbonds or bondwires in parallel to reduce the inductance is reduced by the mutual coupling between them. I'm not sure 0.1 nH of supply inductance is possible.

I suggest you check carefully the values of inductance you expect from your package and the bondwires. My point was it may or may not be a problem depending on how much series resistance you have. Please be sure to at least investigate the issue and simulate it if possible. The last time you want to discover a problem like this is on the bench.

Carl

Title: Re: layout unused area
Post by loose-electron on Sep 28^th, 2007, 2:21pm

adding decoupling capacitance is good - but remember its not the d-couple capacitance that you slam down that you resonate the bond wire with, it is all the capacitance connected to the bondwire that you are dealing with

no longer a nice neat tuned circuit anymore, is it?

give it some thought, the more C on the node the better in my experience

Title: Re: layout unused area
Post by aaron_do on Oct 14^th, 2007, 9:21am

Hi all,

i did a little reading on this, and my understanding is that if i add all this coupling caps from VDD to ground, it will lower the resonant frequency with the bondwire. As a result, high frequency signals will not be able to "escape" the chip. Therefore they will go back through the circuits and be seen as noise. So i should make sure the cap from vdd to ground is not too big...

Is this right?

thanks,
Aaron

Sorry let me correct that...the part about the high frequency signals not being able to "escape" is wrong... so the only problem is that there may be resonance with the bondwire and the coupling cap...

Title: Re: layout unused area
Post by Berti on Oct 14^th, 2007, 10:40pm

Aaron,

The quality factor of a series resonance circuit is given by Q=1/R×√(L/C).
A larger on chip capacitor will therefore result in a lower Q. As a consequence,
the R can also be smaller. Since every capacitor/bondwire has also an series resistor (ESR),
the resonance circuit might become properly damped with enough on-chip capacitance.

High frequency signals won't be seen as noise but will be shorted by the off-chip capacitance.
Therefore actually improving the PSRR of your circuit.

Regards