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Design Languages >> Verilog-AMS >> How to implement induced gate noise current?
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Message started by humble_student on Sep 19^th, 2007, 7:07pm

Title: How to implement induced gate noise current?
Post by humble_student on Sep 19^th, 2007, 7:07pm

Hi all,

I wish to implement noise sources into a RF transistor model. I managed to implement the drain noise current using verilog A with the white noise command. But i am unable to implement the same way for the induced gate noise.

The induced gate noise that i wish to implement includes a resistor in series with a capacitor. How to write it in verilog A to describe such circuit? Thanks.

regds,
humble_student

Title: Re: How to implement induced gate noise current?
Post by Geoffrey_Coram on Sep 24^th, 2007, 7:54am

The MOS11 model I submitted to this website includes correlated noise. Please review the implementation:

http://www.designers-guide.org/VerilogAMS/semiconductors/mos11010/mos11010.va

Title: Re: How to implement induced gate noise current?
Post by humble_student on Sep 24^th, 2007, 8:16am

Dear Sir,

Thanks for your informations. I am trying to understand what you have written in your verilog program of induced gate noise. but as there is no comments in the program, i am afraid that i may interpret wrongly. any other document i can read about your implementation?

Thanks.

Also if possible, may i know how do you check your simulated induced gate noise with your extracted induced gate noise current?

Thanks.

Title: Re: How to implement induced gate noise current?
Post by humble_student on Sep 24^th, 2007, 8:24am

sorry, i didn't write my question clearly.

i am wondering can the induced gate noise current be simulated in Cadence or ADS? if yes, may i know how to do the simulation?

Thanks.

Title: Re: How to implement induced gate noise current?
Post by Geoffrey_Coram on Sep 24^th, 2007, 9:35am

Colin McAndrew and I wrote a paper on correlated noise modeling:
http://www.nsti.org/procs/Nanotech2005WCM/1/T46.03