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Design >> Analog Design >> ON chip LDO
https://designers-guide.org/forum/YaBB.pl?num=1190733187

Message started by rf_jay on Sep 25^th, 2007, 8:13am

Title: ON chip LDO
Post by rf_jay on Sep 25^th, 2007, 8:13am

Hi,

need help in LDO design.

The load is onchip.
When i use a off chip big cap(1uF), the load regulation suffers because of bond pad inductance coming inbetween the load and Cap.

Having a cap onchip more than 300pF is difficult. the load regulation transient still suffers with big spikes. also i need high bandwidth opamp and stability is still an issue.

Please key in your inputs in this regard.

Thanks in advance.

Title: Re: ON chip LDO
Post by carlgrace on Sep 25^th, 2007, 11:41am

rf_jay,

A couple of thoughts that might help.

You can compensate the load regulation issues by adding a zero to your feedback loop. If you put a small value resistor between the output of your op amp and the bondpad, you may find improved transient response.

You can try multiple bondpads in parallel to reduce the series inductance.

You can try to partition the total load cap between a small on-chip local supply, and an off-chip low impedance point. (you may need a buffer between these).

Good luck,
Carl

Title: Re: ON chip LDO
Post by packiaraj on Sep 26^th, 2007, 12:02am

I found a TAMU Thesis that talks about No-External-Cap LDO interesting to read.
Not sure If you had already seen this and how far it's useful for your problem. ;)

Give a read. Link is :
http://txspace.tamu.edu/bitstream/1969.1/3275/1/etd-tamu-2005C-ELEN-Milliken.pdf

Thanks,
Packiaraj.V.