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Design >> RF Design >> LO buffer design
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Message started by aaron_do on Sep 27^th, 2007, 8:49pm

Title: LO buffer design
Post by aaron_do on Sep 27^th, 2007, 8:49pm

Hi all,

anybody have any good ideas on how to design a low power LO buffer? I find that for my low power receiver, the LO buffers require more power than the rest of the system combined.

thanks,
Aaron

Title: Re: LO buffer design
Post by Stefan on Sep 27^th, 2007, 11:32pm

Can you be a little bit more specific ?
Is it that the load the buffers need to drive is so low in resistance or the capacity so high (high current) ?
Maybe it's not the buffer that lead to the problem - is it a single stage or do you have more stages in series to get enough switching speed (What frequency ?) ?

Title: Re: LO buffer design
Post by aaron_do on Sep 28^th, 2007, 1:50am

Hi,

the LO needs to drive a polyphase filter with a few hundred fF. The frequency is 2.4 GHz and i've been using a single stage buffer with inductive loads but i'm open to other possibilities. Also, I had to put the buffer in between the first and second stage of the polyphase filter to avoid signal distortion. So i need 1 buffer for each of the four phases (a lot of power).

Aaron

Title: Re: LO buffer design
Post by asb1211 on Oct 10^th, 2007, 11:08pm

LO buffer reported so far always have very high power dissipation. I don't know in case of your design, but I also have to design LO buffer for passive mixer and for you can refer to commercial product specs or publications.
@ pHEMT 0.5um process, 5V VCC, it always requires a current about 45 mA (see HMC485MS8G datasheet) or @3V VCC, it is 10 mA (see ADL5350 datasheet); @BiCMOS 0.25um process, the current is 9mA to 65 mA when VCC from 1.5 to 5 V (see A SILICON MMIC ACTIVE BALUN/RUFFER AMPLIFIER WITH HIGH LINEARITY AND LOW RESIDUAL PHASE NOISE)