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Design >> Mixed-Signal Design >> Oscillations at DAC output when simulated with I/O
https://designers-guide.org/forum/YaBB.pl?num=1191376514

Message started by venki_vlsi on Oct 2^nd, 2007, 6:55pm

Title: Oscillations at DAC output when simulated with I/O
Post by venki_vlsi on Oct 2^nd, 2007, 6:55pm

Hi,
I am simulating 10 bit DAC without and with including I/O pad (I/O schematic is added).
Simulationg conditions:Fout=10MHz Fclk=125MHz
Setup:An input of 10Mhz input and Fclck=125Mhz to ideal ADC and output of ADC output is connected to MY DAC.
I am getting oscillations with I/O pads.I attached output also.
Can you please suggest me possible reasons.

Title: Re: Oscillations at DAC output when simulated with
Post by carlgrace on Oct 4^th, 2007, 10:26am

Venki,

It is hard to tell what is going on without knowing the internal structure of the DAC. It would appear that the input capacitance of the I/O pad is causing the output buffer of the DAC to become unstable. Can you check its phase margin when it is loaded with the pad?

Carl

Title: Re: Oscillations at DAC output when simulated with
Post by ywguo on Oct 16^th, 2007, 11:47pm

Hi Venki,

Which numerical integration method do you use? HSPICE has 2 options. They are trap, gear. Spectre are more complex. Though method=gear is oftren more accurate than method=gear. It leads to wired oscillation sometimes.

Yawei

Title: Re: Oscillations at DAC output when simulated with
Post by vivkr on Oct 17^th, 2007, 5:59am

ywguo wrote on Oct 16^th, 2007, 11:47pm:

Hi Yawei,

I think you are speaking of oscillations when using integration method=trap. These are usually much smaller if they are present, and limited to
the simulation tolerance. Trap is a more accurate method when simulating stability, as the gear method will cause artificial damping, giving the
impression of stability. In general, if conservative error preset is used, then both methods should give more or less identical results.

I think that this circuit really is unstable and carl has laid his finger on the exact reason. I would check the stability of the buffer with the correct load.

Regards
Vivek

Title: Re: Oscillations at DAC output when simulated with
Post by Ken Kundert on Oct 18^th, 2007, 10:13am

Trapezoidal ringing is point-to-point, meaning that the points will alternate between up and down. The ringing shown in the figure is not point-to-point ringing and so is not trapezoidal ringing. Rather, it is due to the circuit.

-Ken

Title: Re: Oscillations at DAC output when simulated with
Post by sheldon on Oct 18^th, 2007, 9:07pm

Venki,

What type of parasitic model are you using for the pads? Does it
include inductance of the bond wire/package? How are you driving
the pad? Is it driven directly from the DAC output or are you using
a buffer to drive the I/O pads? If you using a buffer, is it stable
with the loading of the I/O?

Best Regards,

Sheldon

Title: Re: Oscillations at DAC output when simulated with
Post by venki_vlsi on Nov 6^th, 2007, 6:42pm

Hi all thanks for replying...

hi yuwei
i am gear2only from cadence-spectre simulator.

Thanks for ur reply.

Hi sheldon
I am designing current steering DAC with 75ohm load.
I am using a bondwire model which includes inductances of 2.6n ,cap of 40f and res of 120m ohm.
I am not using any buffers for driving I/o pads.

Thnaks for reply

hi all

To decrease oscillations ,I added 100pf decoupling capacitor across avdd pins and gnd pin and oscilations got reduced but in the same waveform i am having glitch probem. There was glitch at faling edges but not on rising edges of dac output. This glitch is observed only when [color=#666600]DAC top-level simulations are done with I/O and bond wire models [/color]and no glitch is observed when simulations are done without I/O and bondpad models.This glitch not getiing reduced by increasing the deoupling capacitor.

Please help me in this issuse..

Regards
Venkats

Title: Re: Oscillations at DAC output when simulated with
Post by sheldon on Nov 17^th, 2007, 6:31am

Venki,

The first place to look was the effect of the output parasitics,
however, from your comments it does not seem like they are
the source of the issue.

Here are some things to try:
1) If you simulate with ideal power supplies is the output clean?
--> if the output is clean with ideal supplies then the output
parasitics are not an issue.

It is a little difficult to understand the results with the bypassing,
your comment that the bypass does not effect the glitch may be
correct. However, from looking at the waveforms provided, the
frequency and the magnitude of the ringing seems to be effected
by bypassing.

Questions:
1) What does the output of the reference voltage generator look like?
2) What does the bias line DAC current sources look like?

--> Stabilizing the reference loop can be complex
Does bypassing the reference with a large capacitor effect the
the ringing, for example, 1uF?

3) Are your current switches cascoded?

--> Are the transitions of the current switches kicking back into
the reference line through the Cdg of the current source transistor

4) what do the signal driving the current switch look like?

--> If the buffers driving the current switches are tied to a
digital supply then the digital switching noise could be
leaking into the current switches.

5) Which blocks share power pins?

--> Power supply pins can act a local series feedback between
blocks sharing the pads.

6) Are your current switches, PMOS or NMOS?

--> Grasping at straws, the tail pole shows a directional
dependency, maybe the Cdb of the current source
is providing current /absorbing current resulting in
glitch you observe.

Best Regards,

Sheldon

Title: Re: Oscillations at DAC output when simulated with
Post by loose-electron on Nov 20^th, 2007, 4:52pm

at first glance this looks like inductive ringing in the bond wires.

Take the L associated with the BW and reduce it. See if the oscillation shifts in magnitude and frequency.

Title: Re: Oscillations at DAC output when simulated with
Post by ywguo on Dec 15^th, 2007, 6:17am

Hi Venkat,

It looks a little comlex. The glitch on the transition edge is like that when I simulate IO cell with bondwire. However, there are smaller glitches at the center of each step. I guess that is related to the clock edge. However, the reason is not explicit. Sheldon's advices are probably helpful. Furthermore, the parasitic coupling from the cell that drive the switches to the DAC output are more suspectible.

Best regards,
Yawei

Title: Re: Oscillations at DAC output when simulated with
Post by wyyll on Dec 19^th, 2007, 9:48am

Hi Venkats,

Given the age of this thread, I am hopeful that you have solved your problems, and can post here what the
solution is so we can all learn from it.

In the event not, I have a few points to add.

The noise looks like digital clock noise coupling into your output, perhaps through the digital wires driving the current-steering
differential pairs in your DAC as was suggested. In the small chance you haven't already done this, did you double buffer the
digital control inputs onto your local supplies? Otherwise you inject the noise in your driving ADC into your own DAC. I would also
look for your local clock coupling onto the bias voltage which sets up the currents which are steered. I would also look for the ESD
diodes in your pad schematic to be injecting power supply noise, but this should be common-mode assuming the ESD diode areas
are identical. I mention this last bit because you said adding power supply bypass capacitance reduced the magnitude of the problem

As for the glitches (pink waveform) on falling edges, but not rising, is this a single-ended output, or differential? The signal label IOP suggests it
might be single ended, with the other output IOM not shown, or non-exsistent. For this case, I expect that the cause of the glitch
is the charge-injection associated with turning your current steering switches on and off. For a falling edge, discharging the steering
transistor creates a charge flow opposite to the intended for a short amount of time. For a rising edge, this charge flow would be
of the opposite direction, and might not be visible in your waveform. This typically occurs if you size your current-steering differential pair too
large to get the series resistance down, or the current you are steering is too small. I am not surprised that this shows up only when you add in
the series inductance of the bond wires.

I hope you find this helpful.

Will.

Title: Re: Oscillations at DAC output when simulated with
Post by ywguo on Dec 20^th, 2007, 12:13am

Hi Will,

I don't understand double buffer the digital control inputs onto your local supplies. Would you please explaint it? Thanks.

Yawei