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Simulators >> AMS Simulators >> Viewing subcircuit internal nodes in AMS Designer
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Message started by IVerify on Oct 5th, 2007, 12:11pm

Title: Viewing subcircuit internal nodes in AMS Designer
Post by IVerify on Oct 5th, 2007, 12:11pm

I am unable to view the internal nodes of a Spectre subcircuit in an AMS Designer simulation.  I can only see the nodes that are in Verilog-AMS.  Here's what I have.

top.vams

Code:
`include "constants.vams"
`include "disciplines.vams"
module top ( );
 electrical vdd;
 electrical vss; ground vss;
 sub sub1 (.vdd (vdd), .vss (vss));
 analog V(vdd) <+ 2.5;
endmodule

subcircuit.scs

Code:
//
simulator lang=spectre
subckt sub (vdd vss)
r1 (vdd out) resistor r=1k
r2 (out vss) resistor r=1k
ends sub

top.scs

Code:
tran tran stop=100u save=all
saveNodes options save=all

run.tcl

Code:
database -open output -into out -default
probe -create top -depth all -database output -waveform
probe -create -emptyok -database output -flow -ports -depth all
run 1us
exit

Makefile

Code:
all:  
       rm -rf INCA_libs out
       ncvlog -ams top.vams
       ncelab top -modelpath subcircuit.scs -messages -access +rwc
       ncsim -ams top -analogcontrol top.scs -messages -input run.tcl


When I type:
make
simvision &
I only see top.vdd, top.vss (and the currents).
I want to be able to see sub1.out

Any suggsetions?

Title: Re: Viewing subcircuit internal nodes in AMS Desig
Post by ACWWong on Oct 6th, 2007, 5:42am

If you want to see the node sub1.out (in this case 1.25 volts) then you can do the following:

insert the subckts info control statement into top.scs as follows:

tran tran stop=100u save=all
subckts info what=subckts where=rawfile
saveNodes options save=all

now after running your simulation, you'll get a top.raw results directory.
using wavescan you open the top.raw directory and read the tran.tran results file which will have the sub1.out terminal available for plotting. Unfortunately i don;t think simvision understands the .tran files.... perhaps someone else knows a more elegant method other than making out an explicit terminal ??

cheers
aw


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