The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> use of # in verilog modules in spectreVerilog
https://designers-guide.org/forum/YaBB.pl?num=1191857595

Message started by rajdeep on Oct 8^th, 2007, 8:33am

Title: use of # in verilog modules in spectreVerilog
Post by rajdeep on Oct 8^th, 2007, 8:33am

Hi all,

Is it meaningful to use #50 (delay statements) in a verilog module while simualting with spectreVerilog?
How can we specify the time step (using `timescale) when simualting with spectreVerilog when the timestep for
simulation is decided by the simulator?

Can anyone explain plz?

rajdeep