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Message started by xwj623 on Oct 9th, 2007, 3:12am

Title: Discussion: a ESD structure
Post by xwj623 on Oct 9th, 2007, 3:12am
How does the attached ESD working?  what are the advantages of this structure?
I can't understand  the ESD structure  which have been used in  a company's product.

Title: Re: Discussion: a ESD structure
Post by rajeee1000 on Oct 10th, 2007, 8:40pm
Hi,

I think the functioning of the circuit is as follows:

When the voltage on the input pin increases, the PMOS start conducting. A current proportional to the PMOS's is sucked from the input pin by the NMOS current mirror, reducing the voltage on the input pin.

I am not sure of the pros & cons of the structure.

Regards,
Rajesh

Title: Re: Discussion: a ESD structure
Post by Stefan on Oct 11th, 2007, 12:21am
I think the great deal of this design is that the circuit only protects when AVDD is low.
So it's more a protection for the handling of the chip while bonding or soldering. If the circuit is connected to power supply it will simply look like a small parasitic capacity (from the PMOS) ...

Title: Re: Discussion: a ESD structure
Post by xwj623 on Oct 11th, 2007, 9:02pm
Sorry,I make s mistake.
Thinking carefully, it seems like this...... :)

Stefan wrote on Oct 11th, 2007, 12:21am:
I think the great deal of this design is that the circuit only protects when AVDD is low.
So it's more a protection for the handling of the chip while bonding or soldering. If the circuit is connected to power supply it will simply look like a small parasitic capacity (from the PMOS) ...

Title: Re: Discussion: a ESD structure
Post by SRF Tech on Oct 14th, 2007, 1:29am
Hello xwj623,

 So this is interesting for an I/O protection.  Rajeee understood the operation correctly and stefan correctly noted that the circuit will only function when there is no power, or at least as an active device, passive snapback will still be in effect (which is the case with most ESD protection circuits), now here are a few additional insights i would add.

This is an attempt at using an active clamp (sometimes referred to as FET or BigFET clamp), only these approaches are generally the exclusive domain of power supplies and here is why.  Reasonable ESD currents can be anywhere from ~1.3A (~2kV HBM ideally) to 10A (largest 500V CDM event for most semiconductors).  In order for a fet device to actively clamp such currents in its normal operation, it needs to be a BIG  device.  Most power supply clamps are generally ~1000-5000um wide and have multiple clamps placed on each domain (as a power domain it is feasible to place such large clamps).  The idea is if the clamps can properly conduct the ESD currents under normal operation then everything is good.  Now the I/O are usually protected by a diode to the power supply.  The diode easily handles these large currents and then the current flow down the power bus to the Big FET clamps and get shunted to ground.  Normally placing a BigFET directly on an I/O is prohibitive because of area issues.

With the design you have here, someone figured if they removed the diode and put a big clamp on the I/O itself they will be saving a voltage drop and simplifying the ESD architecture.  Unfortunately what they forgot is that this device as you have it sized (I am assuming with 8 fingers, that are say 50um long at the widest, we are looking at a clamp of maybe 100-400um wide), it will never conduct proper ESD level currents without seeing voltages far beyond its normal range of operation, in which case what we now have is a LV triggered snapback device.

In otherwords even though it looks likes it may be an active device conducting ESD current, because the device is not large enough to conduct full ESD currents it will actually snapback as if it was a grounded gate nmos, only the actual snapback voltage and current will be lower than normal because it will be biased at the gate, similar to a gate-coupled NMOS ESD device.  This is what is likely providing most of the protection.

Hope this helps,
Stephen
SRF Technologies

Title: Re: Discussion: a ESD structure
Post by xwj623 on Oct 15th, 2007, 10:39am
Thank you,SRF.  Very detail. I understand most  of you said.
But I still couldn't understand why the structure didn't function when AVDD was connected to power supply.

For example, AVDD is connected to 5V power supply, when I/O pin is 2KV( HBM), I think the snapback  beakdown  could still happend.  Am I right ?

Thank you.


SRF Tech wrote on Oct 14th, 2007, 1:29am:
Hello xwj623,

 So this is interesting for an I/O protection.  Rajeee understood the operation correctly and stefan correctly noted that the circuit will only function when there is no power, or at least as an active device, passive snapback will still be in effect (which is the case with most ESD protection circuits), now here are a few additional insights i would add.

This is an attempt at using an active clamp (sometimes referred to as FET or BigFET clamp), only these approaches are generally the exclusive domain of power supplies and here is why.  Reasonable ESD currents can be anywhere from ~1.3A (~2kV HBM ideally) to 10A (largest 500V CDM event for most semiconductors).  In order for a fet device to actively clamp such currents in its normal operation, it needs to be a BIG  device.  Most power supply clamps are generally ~1000-5000um wide and have multiple clamps placed on each domain (as a power domain it is feasible to place such large clamps).  The idea is if the clamps can properly conduct the ESD currents under normal operation then everything is good.  Now the I/O are usually protected by a diode to the power supply.  The diode easily handles these large currents and then the current flow down the power bus to the Big FET clamps and get shunted to ground.  Normally placing a BigFET directly on an I/O is prohibitive because of area issues.

With the design you have here, someone figured if they removed the diode and put a big clamp on the I/O itself they will be saving a voltage drop and simplifying the ESD architecture.  Unfortunately what they forgot is that this device as you have it sized (I am assuming with 8 fingers, that are say 50um long at the widest, we are looking at a clamp of maybe 100-400um wide), it will never conduct proper ESD level currents without seeing voltages far beyond its normal range of operation, in which case what we now have is a LV triggered snapback device.

In otherwords even though it looks likes it may be an active device conducting ESD current, because the device is not large enough to conduct full ESD currents it will actually snapback as if it was a grounded gate nmos, only the actual snapback voltage and current will be lower than normal because it will be biased at the gate, similar to a gate-coupled NMOS ESD device.  This is what is likely providing most of the protection.

Hope this helps,
Stephen
SRF Technologies

Title: Re: Discussion: a ESD structure
Post by SRF Tech on Oct 15th, 2007, 11:06am
Hi xwj623,

I was not very clear in this sentence, my mistake:

"stefan correctly noted that the circuit will only function when there is no power, or at least as an active device, passive snapback will still be in effect (which is the case with most ESD protection circuits)"

What I meant by "passive snapback" is exactly what you are asking, yes it will still snapback even with AVDD powered up, only there will be no "active" gate biasing that would lower the snapback voltage, so it would snapback as if it was simply a grounded gate NMOS.

Hope this helps,
Stephen
SRF Technologies

Title: Re: Discussion: a ESD structure
Post by xwj623 on Oct 16th, 2007, 8:09am
Thanks SRF. I understand. :)

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