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Other CAD Tools >> Physical Verification, Extraction and Analysis >> What are these error from LVS: psub_StampErrorMult
https://designers-guide.org/forum/YaBB.pl?num=1192546877

Message started by DoYouLinux on Oct 16^th, 2007, 8:01am

Title: What are these error from LVS: psub_StampErrorMult
Post by DoYouLinux on Oct 16^th, 2007, 8:01am

Hi all,

I tried to run LVS, but I had found the following error messages:

psub_StampErrorMult

psub_StampErrorConnect

Can they be neglected or do we need to set some thing in LVS window (I use Assura) ?

Title: Re: What are these error from LVS: psub_StampError
Post by tosei on Oct 17^th, 2007, 8:49pm

Hi,

I guess these are substrate contacts connected to different nets. That is why is telling you there are multiple stamped connections.
You need to correct this error by looking (most probably) a short between the GND line and some other net.

Hope this helps
Tosei

Title: Re: What are these error from LVS: psub_StampError
Post by bernd on Oct 18^th, 2007, 8:36am

In most of the chip design cases you have more than one ground
net connected to substrate e.g. you have a digital and an analog ground
on your chip. In reality these net might be connect over substrate,
but for Assura LVS these nets have different net names, so it's a kind
of a short over the substrate for the LVS.

Therefore most of the design kits come with a dummy layer to isolate
one part or more parts of the substrate for the LVS, have a look for it.

Or otherwise all your nets connected to substrate should have the same name.

Bernd