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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Cascaded or Single_Loop DSM ADC https://designers-guide.org/forum/YaBB.pl?num=1192606863 Message started by pancho_hideboo on Oct 17th, 2007, 12:41am |
Title: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 17th, 2007, 12:41am Hi. When we consider architectures of DSM(Delta Sigma Modulator) ADC, there are three typical architectures like following. (1) High Order Single Loop (2) Cascaded (MASH) (3) Hybrid of (1) and (2) If we consider power consumption, occupied area, device mismatch, DT(Discrete Time such as SCF), CT(Continuous Time), stability and SNQR issues, above three architecture candidates have merits and demerits each other. It seems that cascaded type DSM ADC is not so popular in actual product. I know that device mismatch effect is severe in (2). But about stability, (2) is superior than (1). Why is not Cascaded DSM ADC popular ? |
Title: Re: Cascaded or Single_Loop DSM ADC Post by Berti on Oct 17th, 2007, 3:43am Hey, Quote:
what do you mean with hybrid converter? Because a cascaded modulator with high order first stage doesn't make sense. I think the reasons that there are not so many cascaded modulators are:
Regards |
Title: Re: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 17th, 2007, 4:01am Thanks for response. Hybrid I'm meaning is for example, three cascaded stages like following. 1st-order + 1st-order + 2nd-order(single-loop) It seems multibit with DEM is most high performance and main stream of DSM ADC. |
Title: Re: Cascaded or Single_Loop DSM ADC Post by Berti on Oct 17th, 2007, 7:29am I think so.... ...but on the other hand I also think that people often do such decisions according to "unscientific" statements like "cascaded modulators suffer from noise-leakage" or "CT modulator consume less power than DT". Maybe that's why CT single-loop is so popular..?.. In theory this might be true. But many CT modulators consume more power than DT modulators because of wrong design decisions. Therefore depending on the specifications, a cascaded modulator might also be good choice (and a good design won't suffer from noise leakage). As you correctly wrote: Quote:
Regards |
Title: Re: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 17th, 2007, 8:45am Hi. I think CT cascaded DSM is very difficult to design. So cascaded architecture almost require implementation as DT(SCF). I still want to pursue any possibility of 1bit quantizer. :P |
Title: Re: Cascaded or Single_Loop DSM ADC Post by Berti on Oct 17th, 2007, 10:18pm Hey, consider the design of a tri-level quantizer instead of a 1bit quantizer. As long you make sure that the offset of the amplifier is always transfered, a tri-level quantizer is inherently linear but drastically reduces quantization noise compared to 1 bit. Regards |
Title: Re: Cascaded or Single_Loop DSM ADC Post by vivkr on Oct 18th, 2007, 2:45am Berti wrote on Oct 17th, 2007, 10:18pm:
Hi Berti, Could you please elaborate on this point? Why would a tri-level quantizer drastically improve quantization noise? If one purely considers the number of quantization levels, not much has changed. Are you implying that the linearization of the quantizer characteristic allows larger input signal without impairing stability, or is there some other reason? One reason I can see is that the presence of 3 levels would mean that the quantizer output idles around the mid-level most of the time when the input signal is very small, thereby reducing the amount of out-ofband noise that needs filtering, but this would not hold for larger signals. Hi Pancho, Also consider multibit quantizers and single-loop DSM. With mismatch shaping and dithering, you can get excellent performance and the design is considerably simplified. Regards Vivek |
Title: Re: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 18th, 2007, 3:24am Hi, vivkr. I think multibit with DEM must be most high performance and main stream of DSM ADC. But I'm considering adopting DSM to RF signal. So low resolution quantizer(feedback DAC) is preferable. |
Title: Re: Cascaded or Single_Loop DSM ADC Post by Berti on Oct 18th, 2007, 5:25am Hi Vivek, As you wrote: a) A tri-level quantizers increases the max.input signal b) The mid-level reduces the output power of the quantizer. See the paper: J.J.Paulos et.al., "Improved Signal-to-Noise Ratio Using Tri-Level Delta-Sigma Modulation", IEEE Proceedings of the Int. Symp. on Circ. and Systems, May 1987. Pancho, what sampling-rate do you plan for modulator? Regards |
Title: Re: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 18th, 2007, 9:17pm Hi, Berti. I plan to sample at about 1GHz. So I think DT(SCF) modulator result in large power consumption. I read old paper you teach about Tri-Level Delta-Sigma Modulation if I can get it. |
Title: Re: Cascaded or Single_Loop DSM ADC Post by vivkr on Oct 18th, 2007, 11:07pm Hi Pancho, I doubt if sampling a DT SCF based modulator at 1 GHz will lead to a very efficient design. Maybe it really is worthwhile considering the use of a CT modulator, especially if you are only interested in a narrowband of signals around RF. You could use a bandpass modulator. It will probably be much more power-efficient and effective even with additional circuits for removing process variations of the coefficients and for generating an on-chip frequency. A very good paper on a similar topic is to be found in JSSC, Dec. '06 by Mitteregger et al. A 20-mW 640-MHz CMOS Continuous-Time SigmaDelta ADC With 20-MHz Signal Bandwidth; 80-dB Dynamic Range and 12-bit ENOB The authors there use a CT DSM but decimate down the output on-chip to get an effective Nyquist bandwidth of about 20 MHz at baseband. From a system and circuit design point of view, this is an excellent ADC scheme. You could make good use of the applied principles here. Regards Vivek |
Title: Re: Cascaded or Single_Loop DSM ADC Post by pancho_hideboo on Oct 22nd, 2007, 12:29am Hi, Vivek. Of course, I know CT-DSM you refer. This DSM is published at ISSCC 2006. Features of this ADC are 4bit-3rd-Order-CT-DSM using NRZ-DAC with combination of Feedback and Feedforward. I know 4bit quantizer is main stream in current DSM ADC. The following paper's DSM ADC is also 4bit. Richard Screier, et al.,"A 375mW Quadrature Bandpass DSM ADC with 90dB DR 8.5MHz BW at 44MHz", ISSCC 2006. As I said in previous post, I still want to pursue any possibility of 1bit or less resolution quantizer. I have interests in the approaches of following papers. B.Putter, "A 5th-order CT/DT Multi-Mode DSM Modulator", ISSCC 2007. Lucien J.Breems, et al., "A 56mW CT Quadrature Cascaded SDM Modulator with 77dB DR in a Near Zero-IF 20MHz Band", ISSCC 2007. |
Title: Re: Cascaded or Single_Loop DSM ADC Post by Berti on Oct 22nd, 2007, 1:58am Hi Pancho, I guess that your amplifier will require a very high bandwidth to avoid phase shift (-> excess loop delay). The nested-miller amplifier used by Mitteregger can provide very high bandwidth at reasonable current. The other papers your mention (Putter and Breems) use a SC DAC. I think that solution will consume more power (higher bandwidth for settling required) and probably prohibits the use of a nested-miller amplifiers (pole-zero doublet deterioate settling). On the other hand using a 1bit quantizer might result in very tough jitter requirements. A multi-bit quantizer could relax that.... Regards |
Title: Re: Cascaded or Single_Loop DSM ADC Post by vivkr on Oct 23rd, 2007, 12:01am Hi Pancho, Berti makes some important points. An SC-DSM would be a very hard undertaking from every front, and a 1-bit quantizer also would make life much harder. Please note the various things that Mitteregger et al. have done. I will point out the key points I saw inthat paper: 1. Use of CT DSM + mild input antialias filtering (not mentioned but there must be atleast some) implies that system works in CT mode, that is no steps or any sharp transients on the input. 2. Since system is CT with no transients, it is possible to use pole-zero compensation in the opamp to achieve wide bandwidth. No transients => step response not important, only steady-state response => bandwidth only needs to be much much lower => lower noise, lower power. 3. Use of a latch in the DAC feedback path => comparator metastability not important. This in reality is a much larger contributor to DAC jitter than just the clock jitter (see papers by Cherry & Snelgrove on this topic). The half-cycle delay is compensated in the loop filter itself, and should partially reduce sensitivity to phase delay in the opamps (atleast to my understanding but I may be wrong on this point). You can use methods to shape mismatch in a multibit DAC. Of course, if you are constrained to use a 1-bit quantizer due to system restrictions, then it is another story. Maybe some SDM experts can add their comments here. Regards Vivek |
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