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Design Languages >> Verilog-AMS >> Array declaration for analog output
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Message started by shaikhsarfraz on Oct 17^th, 2007, 10:28pm

Title: Array declaration for analog output
Post by shaikhsarfraz on Oct 17^th, 2007, 10:28pm

Hi All,
Is it possible to declare an analog output array of a sensor block in verilog - ams?

Here is what I am doing

module XYZ (in,out);

output [Array_size-1:0] out;

Now how to declare this output out net i.e whether to use wreal or electrical or is there any other assignment.
The port out is supposed to carry analog signals.

Regards
Sarfraz

Title: Re: Array declaration for analog output
Post by jbdavid on Nov 30^th, 2007, 1:38pm

If "out" is wreal you'll have to declare an array of real, and do an assignment from the real array to the wreal array,
if "out" is electrical, you'll have to create a contribution statement for each wire in the bus.
jbd