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Design >> Mixed-Signal Design >> Ask for help about Guard-ring in SoC
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Message started by rf_usn on Oct 19^th, 2007, 12:08am

Title: Ask for help about Guard-ring in SoC
Post by rf_usn on Oct 19^th, 2007, 12:08am

Hi all,

I am a beginer in SoC field.
I am looking for any documentd, books in which they discuss about Guard-ring rule in SoC. Can anyone help me about that?

Thank you very much in advance.

Regards,

rf_usn.

Title: Re: Ask for help about Guard-ring in SoC
Post by SRF Tech on Oct 24^th, 2007, 12:11pm

I can not think of any one particular I would recommend at the moment, but I will offer basic advice that I have come to understand thru both my own research projects and experiences as well as those of others I have known and worked with.

Guard Rings generally serve two purposes:

1. Noise Isolation
2. Latchup and ESD Protection

A few basic comments regarding both:

I. Noise Isolation:

1. If the guardring does not have a low resistance/impedance/inductance strap to the primary power busses, it will not be effective.
The effectiveness of the guardring to shunt noise is determined by its impedance as seen by the noise, poor or highly resistive/impedance connections effectively isolate the guardring from the quiet supplies. Use lots of contacts, vias and metal getting the guardring connections to the power/GND supplies to which you want to shunt noise.
(In other words do NOT route a nice fully contacted guardring and then on the very far corner have a 2-4 via jumper to a minimum width metal line that runs 100's of ums to a power supply...you basically rendered the ring useless).

2. Double guardrings are more effective than single, triple are not much more effective than double and quadruple guardrings basically serve the unique purpose of wasting silicon space. Use double guardrings but do not waste much more area beyond that.

3. Distance is Key!! The closer your guardring is to the circuit you are protecting the better it will work! (Thus the ineffectiveness of quadruple guardrings who are generally further away). The rings should be laid out at nearly minimum distances from the sensitive nodes assuming you are not running into capacitance issues. Also they should conform to the shape of the sensitive circuit, not just be a big square, in order to maximize effectiveness.

4. Offense is better than defense! What do I mean by this? It means that you will do a much better job of picking up substrate noise by guardringing your aggressors than you will by guardringing your victims. Its not to say that it does not help, but studies I have been privy to have shown that there is substantial benefit by focusing on the noise generators while placing guardrings. Granted this can be hard to accomplish when the main aggressor is a large digital block. Of course your always better off if you guardring both aggressors and victims.

II. Latchup and ESD

1. Similar to Noise isolation, resistance/impedance is key so make sure the rings are definitely strapped into the power/GND busses, not some anemic 2 via minimum width metal route.

2. Double guardrings are very effective and anything else is generally unnecessary.

3. Generally, only nodes directly connected to the Pad/Bump or capacitively coupled (input gates or AC coupling cap or even parasitic cap) to the pad/bump should really be concerned about latchup. There are always exceptions for certain internal nodes but this tends to be the general rule.

4. Only included devices connected to the latchup risk nodes in a guardring!! (i.e if you have a double guardring wrapped around an output driver, make sure there are no control logic or enable logic devices included inside the primary ring...this can be very risky!

5. Never place two N+ rings next to each other without a low resistance P+ ring in between! Especially if the N+ rings are at different potentials, otherwise you are just begging for a parasitic NPN latchup event. I can't tell you how many times I have found this to be a problem in a clients product!

6. Pay extra attention to PMOS and NMOS spacings when doing your guardringing of output devices. Never EVER guardring them together even if they are part of the same driver! If you guardring your PMOS and NMOS devices together you have just taken an extra step towards ensuring a latchup event. (This is basic

I will stop with these, I am sure other have very insightful comments as well.

Stephen
SRF Technologies

Title: Re: Ask for help about Guard-ring in SoC
Post by rf_usn on Oct 24^th, 2007, 6:37pm

Dear SRF Tech,

Thank you very much for your help. Those are useful informations for me at this time.

Best regards

usn_rf

Title: Re: Ask for help about Guard-ring in SoC
Post by Berti on Oct 25^th, 2007, 12:51am

Hi Stephen,

can you please elaborate on ESD and Latch-up point 4?

Quote:

4. Only included devices connected to the latchup risk nodes in a guardring!! (i.e if you have a double guardring wrapped around an output driver, make sure there are no control logic or enable logic devices included inside the primary ring...this can be very risky!

It's not so clear to me.

Thanks

Title: Re: Ask for help about Guard-ring in SoC
Post by SRF Tech on Oct 25^th, 2007, 10:35am

Hi Berti,
What I mean is that when you are wrapping a guardring around a device, say and nmos output driver, make sure there are no other devices included within that same guardring, such as say an nmos predriver device.

Negative Example: A tendency that I see happen is a mask designer will layout out the output driver and then the predriver and then guardring them together, that is exactly what I am saying you need to avoid.

Positive example: You have a pad node that feeds an output driver, a pass-gate and an input NMOS transistor. The guardring ideal would be:

Output driver: PMOS devices in their own guardrings-Double
NMOS devices in their own double guardring

Pass-Gate: Guardring the PMOS and NMOS devices individually and separately. (Note multiples or fingers of the same device can be guardringed together.)

Input transistor: Sits in his own guardring.

Each guardring only contains the devices listed and none other. No predriver circuits, no enable circuits, no logic nothing...note that some of these other devices may need their own guardrings, but you can not share guardrings for high risk nodes is what I am trying to say.

Does this help?
Thanks,
Stephen
SRF Technologies

Title: Re: Ask for help about Guard-ring in SoC
Post by Berti on Oct 26^th, 2007, 1:33am

Thank you Stephen, I think I got the point.

Regards

Title: Re: Ask for help about Guard-ring in SoC
Post by loose-electron on Nov 20^th, 2007, 5:04pm

Guard rings dont help a whole heck of a lot (based upon a thorough lab study of real world test cases done at IBM, while I was there) - may I suggest reading some on interference noise - read this 2 part articles linked here:

http://www.effectiveelectrons.com/JerryTwomey.htm

on there is a 2 part article I did for Electronic Design on the topic.

Jerry

Title: Re: Ask for help about Guard-ring in SoC
Post by ywguo on Dec 2^nd, 2007, 6:35am

Hi Stephen,

Quote:

Use lots of contacts, vias and metal getting the guardring connections to the power/GND supplies to which you want to shunt noise.

When I have enough pins, the guardring is connected to a pair of special power/GND supplies which is quiet and for guardring only. However, I am always pondering whether the guardring is connected to analog power/GND or digital power/GND when I have not any power/GND for guardring only. I often guardring analog part because the digital block is huge. So the substrate noise pollute the power/GND if the guarding is connected to analog power/GND. But the sensitive analog circuitry is interfered if the guardring is connected to dirty digital power/GND and very near, isn't it? :-/

Best regards,
Yawei

Title: Re: Ask for help about Guard-ring in SoC
Post by wyyll on Dec 3^rd, 2007, 6:21am

Here are my 2 cents worth.

As Stephen pointed out, it is all about identifying the aggressors and the victims.

Guard Rings when placed correctly do one of the following, or both.
a) provide a lower impedance path to a dump node/power supply.
b) increase the impedance between the aggressor and victim.

One needs to be careful in the selection of the dump node, in that it too can become an aggressor.
Tying your Guard Ring to a supply with its own noise sources different from the ones you were worrying
about means you just added a new aggressor.

From what I have seen and read, I agree with Jerry that guard rings are not the be-all and end-all for getting
rid of pesky noise problems. They do however increase the distance between aggressor and victim, without appearing
as white space. Thanks for the link.

I do use them, a lot. I put them between my analog macro, and the digital logic on the ASIC. I tie them off
locally, so they don't become an aggressor. As for isolating my own blocks from each other within the macro, I find
sometimes a good set of tub ties is a more effective solution.

Will

Title: Re: Ask for help about Guard-ring in SoC
Post by loose-electron on Dec 11^th, 2007, 12:42pm

wyyll wrote on Dec 3^rd, 2007, 6:21am:

From what I have seen and read, I agree with Jerry that guard rings are not the be-all and end-all for getting
rid of pesky noise problems. They do however increase the distance between aggressor and victim, without appearing
as white space. Thanks for the link.

The ED article, even as a 2 part series, had to be watered down a lot to get it published. Key thing here is a comprehensive and distributed approach to noise, not just slapping a few guard rings down and keeping your fingers crossed.

With all the discussion and black magic opinions on guard rings swirling around, we did a foundry based study and got a bunch of empirical data in the lab. It made a lot of people stop thinking of rings as the universal noise fix.

Key thing to remeber - rings are only 1-2 microns deep, noise goes underneath these, so you havent built a perfect wall. I do a PPT on the topic as part of industry training, and rings are only a small part of a methodology that includes -- grounding, shielding, differential systems, path balancing, reducing generation sources, physical seperation, time and frequency division, impedance of power and ground, distributed filtering, selective bandwidth limiting, and a multitiude of others.

The talker/listener, (aggressor/victim, or whatever name you like) is a good approach, but is only the starting point.
Interference noise has been a big part of my technical design efforts, but the interesting thing is that I generally get dragged into the issue after somebody has a DOA chip due to noise. Beter to train the team prior to design. Its a training seminar that pays for itself multiple time over.