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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Help needed for modelling a sensor block in VAMS https://designers-guide.org/forum/YaBB.pl?num=1193240891 Message started by shaikh_sarfraz on Oct 24th, 2007, 8:48am |
Title: Help needed for modelling a sensor block in VAMS Post by shaikh_sarfraz on Oct 24th, 2007, 8:48am Hi, I have to model a sensor block in Verilog-AMS. The problem is some thing like this: I have 32 arrays of real values. Each array holds 40 real values. A0[39:0]= 3 a 4 5 2...............e 1 A1[39:0]=............................... .............................................. .............................................. A31[39:0]=..........................d 6 Now I have to select each array and take each real value in that array at a time and after some processing assign it into output analog port. The statements will look like this electrical [39:0] OUT genvar i,j; real dp,pd; /*There will be 32 real arrays declared*/ real [39:0] A1; real [39:0] A2; ....... ....... real [39:0] A32; analog@(initial_step) begin for (i=0;i<32;i = i+1) begin if (i == 0) begin for (j=0;j<40;j = j+1) begin dp = A0[j] ; pd = 1.5 - 1.05 - dp/55; V(OUT[j]) <+ pd; end end if (i == 1) begin for (j=0;j<40;j = j+1) begin dp = A1[j] ; pd = 1.5 - 1.05 - dp/55; V(OUT[j]) <+ pd; end end ........ ......... ....../*Here we will assign each real array(A0[39:0], A1[39:0]......A31[39:0]) to the output port (OUT[39:0]) one at a time, so there will be 32 if statements for passing 32 real arrays*/ if (i == 31) begin for (j=0;j<40;j = j+1) begin dp = A31[j] ; pd = 1.5 - 1.05 - dp/55; V(OUT[j]) <+ pd; end end end end Here is the list of problems which we are facing: 1). We cannot assign electrical (analog) ports (OUT[39:0]) inside for loop. 2). To solve this problem we used generate statement. But we cannot use nested generate loop. In short our problem is that we have 32 arrays with each array holding 40 real values. Now we have to pass each of these 40 real values to the 40 bit analog output. And in between we have to process (manipulations) each of these 40 real values , so it requires nested loops. It seems like the Verilog-AMS language (and AMS simulators) has few limitations due to which this problem is not getting solved. I will appreciate any help for any body for providing any work around for this problem. Regards Sarfraz |
Title: Re: Help needed for modelling a sensor block in VA Post by Geoffrey_Coram on Oct 24th, 2007, 12:21pm I think you probably *don't* want the contribution statements V(OUT[j]) <+ pd; to be inside if statements. I would suggest you create a real array vout, add up all the values from the different i,j blocks in nested for-loops, and then do the contribution in a single generate loop at the end. (Is it V-AMS that prohibits nested generate loops, or your simulator?) |
Title: Re: Help needed for modelling a sensor block in VA Post by shaikh_sarfraz on Oct 24th, 2007, 9:28pm Thanks for the suggestion.....I will try it out and see if it succeeds.... :) Regarding the nested generate statements: I am using Cadence AMS Designer suite. Here I am getting error during complation stage saying that "Affirma AMS doesnot support nested generate statement" So the toll doesnot supports it. Also when I checked with Accellera VerilogAMS manual, it says generate statements are obsolete. Regards Sarfraz |
Title: Re: Help needed for modelling a sensor block in VA Post by Geoffrey_Coram on Oct 30th, 2007, 11:37am shaikh_sarfraz wrote on Oct 24th, 2007, 9:28pm:
Not really relevant here (you just care about what your tool supports now): I think the original "generate" construct in Verilog-AMS (1.0? 2.0?) is obsolete, but a new generate is coming in LRM 2.3 and is based on some 1364-2005 definition of the construct to be compatible with SystemVerilog. |
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