The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Semiconductor Devices >> MOSIS ring oscillator test structure
https://designers-guide.org/forum/YaBB.pl?num=1193413105

Message started by jeremy on Oct 26^th, 2007, 8:38am

Title: MOSIS ring oscillator test structure
Post by jeremy on Oct 26^th, 2007, 8:38am

I'm not sure if this is the right forum, but here goes: MOSIS has pages like this one (http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/t77a_mm_non_epi_thk_hr8-params.txt) for the process they work with, and there is a section containing ring oscillator power and frequency measurements. Does anyone know what test structure they use to come up with these numbers? When I try to duplicate the measurements in simulation with a ring oscillator of minimum-sized inverters (Wn=Wmin; Wp=2*Wmin), I come up with about 4x less power and about 40% higher frequency than they do.

The lines I'm talking about look like this:
DIV1024 (31-stg,1.8V) 0.02 uW/MHz/gate
which made me think maybe DIV1024 is a standard structure, but I haven't been able to find anything on it.

Thanks,
Jeremy

Title: Re: MOSIS ring oscillator test structure
Post by Frank Wiedmann on Oct 27^th, 2007, 1:23pm

You might get closer to the measured results if you include realistic wiring capacitances in your simulation.

Title: Re: MOSIS ring oscillator test structure
Post by krishnap on Nov 28^th, 2007, 3:15am

I think this is the divide by 10 structure where input clock is devided by 1024 after 10 stages.