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Design Languages >> Verilog-AMS >> Instantiating a Spectre source in Verilog-A
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Message started by Croaker on Nov 5^th, 2007, 1:24pm

Title: Instantiating a Spectre source in Verilog-A
Post by Croaker on Nov 5^th, 2007, 1:24pm

Hello, I am trying to instantiate a Spectre voltage pulse source in my Verilog-A code like so:
vsource #( .type("pulse"), .val0( vss ), .val1( vdd ), .delay( tdel ), .rise( trise ), .fall( tfall ), .width( twidth ), .period( tperiod ) ) v1( a, b );

I get the error that "delay" is a reserved name of a simulator library function.

How can I instantiate this module without running into this delay error? It seems I must pass the parameters this way, as just passing the values in order doesn't work.

Help!

:'(

Title: Re: Instantiating a Spectre source in Verilog-A
Post by Geoffrey_Coram on Nov 6^th, 2007, 6:06am

Annex E of the Verilog-A LRM says you should do:

vpulse #(.val0( vss ), .val1( vdd ), .td( tdel ), .rise( trise ), .fall( tfall ), .width( twidth ), .period( tperiod ) ) v1( a, b );

Title: Re: Instantiating a Spectre source in Verilog-A
Post by Croaker on Nov 7^th, 2007, 11:27am

Thank you! I did some digging and found another workaround. The reserved function 'delay' must be escaped, like so:

.\delay ( tdel )

Put a '\' before the word and a ' ' (space) after it.

Cheers! :)