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Simulators >> RF Simulators >> VerilogA erases clock phase noise with PNOISE
https://designers-guide.org/forum/YaBB.pl?num=1194372415

Message started by adam_eaz on Nov 6^th, 2007, 10:06am

Title: VerilogA erases clock phase noise with PNOISE
Post by adam_eaz on Nov 6^th, 2007, 10:06am

I am applying a differential clock signal as an input which has some phase noise, and I am producing a differential clock signal that has a fixed pulse width. The problem is that the resulting signal doesn't have any phase noise. The PSS analysis does work, with the correct wave forms produced.

`include "constants.vams"
`include "disciplines.vams"

module xosc10b_amfilter (inp, inm, outp, outm);

input inm, inp;
inout outm, outp;
voltage inm, inp, outp, outm, vgain;

parameter real vswing=1;
parameter real td=50p;
parameter real tt=50p;
parameter real delaytime=6.4300412n;
real vtime, vmin, vmax;
integer actNow, out, reset;

analog
begin
actNow=0;
vmin=-vswing/2;
vmax=vswing/2;

@(cross(V(inp,inm),1)) actNow=1;

vtime= idt(1/delaytime, 0, actNow);
out = vtime<1;

V(outp,outm) <+ transition(out ? vmax : vmin, td, tt);
end
endmodule

Title: Re: VerilogA erases clock phase noise with PNOISE
Post by Stefan on Nov 6^th, 2007, 10:17am

You should (dramatically!) increase your analog accuracy-settings and specify the tolerance of the @cross statement.
td and tt are far too high with 50 ps. This would kill nearly all phasenoise characteristics.

Just think about an oscillator with a center frequency of 2.4GHz for Bluetooth for example.
Specifications for the LO demand for -105 dBc/Hz at 1 Mhz offset from the carrier which leads to a corresponding Jitter (standard deviation) of around 48 fs.
It's for sure that an accuracy of several ps simply swallows this noise ...

Title: Re: VerilogA erases clock phase noise with PNOISE
Post by adam_eaz on Nov 6^th, 2007, 11:50am

I tried your suggestion of increasing the analog accuracy and cross point. I also changed the rise time to 200ps, but I am still getting the same result which is -6.4k dBc for all frequencies. Any other suggestions?

Adam

Title: Re: VerilogA erases clock phase noise with PNOISE
Post by Stefan on Nov 6^th, 2007, 1:35pm

You should tighten the rise time, not raising it.
It might be best to provide the whole setup, including the model for the noisy osc.
I might be able to check it tomorrow morning (local time central europe).
Regards,

Stefan

Title: Re: VerilogA erases clock phase noise with PNOISE
Post by Frank Wiedmann on Nov 6^th, 2007, 11:29pm

See http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426/5#5.