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Design >> Mixed-Signal Design >> thd of buffer post DAC
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Message started by cmos_cowboy on Nov 7^th, 2007, 2:30pm

Title: thd of buffer post DAC
Post by cmos_cowboy on Nov 7^th, 2007, 2:30pm

I have a DAC that is designed to give 10bit accuracy.
It requires a unity gain buffer to drive a capacitive load.
If I do not want the buffer to degrade the DAC output by more
than say 0.5 lsb I am correct in assuming that -
0.5/1024 gives rise to a THD spec of -66dB.
Am I correct in my assumptions or is it a little more complicated?

Title: Re: thd of buffer post DAC
Post by cktlife on Nov 8^th, 2007, 12:38am

I have the same question for the cascaded system. In this case, two blocks are in series, DAC+buffer. Suppose that the overall 10-bit accuracy is wanted, how do i allocate the linearity requirement for each block? Is there any analytical solution or just emperical estimation?

Title: Re: thd of buffer post DAC
Post by Berti on Nov 8^th, 2007, 10:51pm

Hi everybody,

how to calculate the linearity of cascaded systems can be found in text-books (similar to Friis' formula).
In case of a DAC+buffer combination I think the question is whether you want the linearity limited by
the DAC, the buffer or a combination of both.
Usually the liniearity should be limited by the DAC. The buffer should therefore be linear enough not to
degrade the overall linearity to much.

Regards