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Design Languages >> Verilog-AMS >> Instantiating a model in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1195009648

Message started by IVerify on Nov 13^th, 2007, 7:07pm

Title: Instantiating a model in Verilog-A
Post by IVerify on Nov 13^th, 2007, 7:07pm

I'm trying to instantiate a model in Verilog-A where the cell name is different than the model name.

For example:
Library Name: lib
Cell Name: foundry_cell
View Name: symbol
Under CDF parameter
Model name: model_of_cell

In Verilog-A, I tried:
foundry_cell #(.param1...) (.node1(x)...);

When doing this the elaborator says "Cannot find any unit under lib:foundry_cell:symbol in the design libraries". This makes sense as it has no way of knowing the mapping from foundry_cell to model_of_cell. I also tried:

model_of_cell #(.param1...)(.node1(x)...);

This doesn't work, because there is no cell view called "model of cell"

Is there a way I can specify the model name when I instantiate "foundry_cell" in Verilog-A? Is there a parameter for model name that I can use?

-I Verify

Title: Re: Instantiating a model in Verilog-A
Post by IVerify on Nov 15^th, 2007, 11:27am

Instantiating the cell in this way seemed to work.

model_of_cell #(.param1...) (* integer library_binding = "lib"; *) instance_name (.node1(x)...);

The hierarchy editor will complain that "model_of_cell" cannot be found, but the simulation will run.