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Design >> Analog Design >> phase inversion in comparators
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Message started by vivkr on Nov 14^th, 2007, 11:01pm

Title: phase inversion in comparators
Post by vivkr on Nov 14^th, 2007, 11:01pm

Hi,

Please see Fig. 10 on page 4 of AN-849. What are the reasons
for phase inversion in comparators? Is this specific to technology
or device type?

http://www.analog.com/UploadedFiles/Application_Notes/46875282066493AN_849.pdf

Regards
Vivek

Title: Re: phase inversion in comparators
Post by imd1 on Nov 15^th, 2007, 1:33am

It depends on the architecture of the output stage of the opamp, I think. In older (and some current also ?) CMOS opamps the output will "peg" to a supply rail (always the same) when the common-mode range at the input is exceeded.

Use a comparator if you are comparing, opamps are always much slower...

Title: Re: phase inversion in comparators
Post by vivkr on Nov 15^th, 2007, 4:21am

Hi,

I am not planning to use an opamp as a comparator but was just cuious as to how such a phase inversion could occur.
Are you saying that if the common mode changes beyond a certain point, then the input stage turns off and the output
is then pegged high/low depending on the output stage?

It would be interesting to see an example of such a circuit. One can always do with a list of "DON'T USE" circuits.
Could you post an example?

Thanks
Vivek

Title: Re: phase inversion in comparators
Post by loose-electron on Nov 15^th, 2007, 10:48am

This is, how shall I say it, totally unique to the transistor level architecture of the comparator.

Rail to rail common mode comparators are possible (both an NMOS and PMOS diff pair at the input, and some recombination circuitry afterwards) and all kinds of other variations on a theme.

Specifying a common mode range and operating limitations should not be a problem in most cases.