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Modeling >> Behavioral Models >> A wield problem in behavior model simulation
https://designers-guide.org/forum/YaBB.pl?num=1195179416

Message started by jimwest on Nov 15^th, 2007, 6:16pm

Title: A wield problem in behavior model simulation
Post by jimwest on Nov 15^th, 2007, 6:16pm

I built a gated pll for CDR in serdes.
Every block was implemented in verilog-a. And the structure is shown in Fig.1.

When the gated vco was disabled, everything is ok. The control voltage which is highlighted in Fig.1 is shown in Fig2.

At the moment when the gated vco was enabled while the pll locked, there is a bump in control voltage and the pll will be locked at another freq as shown in Fig3.

I just wonder What introduces this wield step in control voltage.
And I tried to use different method and different simulator this bump can not be eliminated.

Title: Re: A wield problem in behavior model simulation
Post by jimwest on Nov 15^th, 2007, 6:19pm

Fig2

Title: Re: A wield problem in behavior model simulation
Post by jimwest on Nov 15^th, 2007, 6:22pm

Fig.3

Title: Re: A wield problem in behavior model simulation
Post by Stefan on Nov 16^th, 2007, 12:32am

The schematic is hard to understand, especially because you didn't label any of the signals.
The only thing I'm wondering about at first sight is that you're missing a clearly defined VDD node.

Title: Re: A wield problem in behavior model simulation
Post by Stefan on Nov 16^th, 2007, 12:34am

and another thing ... maybe you should try to use a vcvs to couple the second oscillator to the control voltage. Maybe it's just some sort of current source problem coming from the CP/LF ?

Title: Re: A wield problem in behavior model simulation
Post by jimwest on Nov 16^th, 2007, 9:23pm

The vcvs has been used to isolate the gated vco and pll, but this bump is still there.
I skip the dc analyze when do the transient simulation, so no VDD should be set.