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Design >> Mixed-Signal Design >> Production Test of 3rd order delta sigma adc/dac i
https://designers-guide.org/forum/YaBB.pl?num=1195215954

Message started by babug on Nov 16^th, 2007, 4:25am

Title: Production Test of 3rd order delta sigma adc/dac i
Post by babug on Nov 16^th, 2007, 4:25am

I am trying to add some DFT features on chip to test 3rd order delta sigma adc/dac in codec application.
The ATE we use is not mixed signal ATE, it is digital; which makes me rely on the DFT/BIST added to thoroughly test the ADC/DAC.
My understanding is that,
Digital portion of the ADC and DAC are tested by standard digital dft techniques (scan/bist).
What are the ways to test analog portion on chip?
I see an issue in generation of analog stimuli on chip?
Also, what are the necessary and sufficient adc/dac parameters that needs to be measured (on chip) to qualify the production test?