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Modeling >> Behavioral Models >> sample-and-hold by noisy clock
https://designers-guide.org/forum/YaBB.pl?num=1195250701

Message started by Aigneryu on Nov 16^th, 2007, 2:05pm

Title: sample-and-hold by noisy clock
Post by Aigneryu on Nov 16^th, 2007, 2:05pm

Hi,

I am trying to build a vlog-a model that can be used in PSS, Pnoise. And it can let the noise pass through the clock port.
Ken's S/H model can be used in PSS, but cannot reflect the noise effect from clock port. I found there is no easy way to do this
because level/transition detection cannot be utilized. In other words, I cannot rely on event detection any more.

Another simpler example is to build a DFF with this kind of property. In that case, I have to build an "almost-real" model by hooking up inverters, latches with gain compression, and capacitive loading.

Again, this appraoch is straightforward, but very inefficient, does any one have some suggestions? Sometimes if a model needs to be compatible with PSS (free from hidden state), it is very difficult to have the efficiency and physical meaning at the same time, such as the frequency divider without hidden-state.

Regards.