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Modeling >> Semiconductor Devices >> single layer oxide deposition process
https://designers-guide.org/forum/YaBB.pl?num=1195815016

Message started by vivkr on Nov 23^rd, 2007, 2:50am

Title: single layer oxide deposition process
Post by vivkr on Nov 23^rd, 2007, 2:50am

http://www.spectrum.ieee.org/oct07/5553

The above article describes how Intel engineered their latest transistors in 45 nm.
One small point mentioned is that the oxide layer is grown one atomic layer at a time,
and this process is perfectly controllable. Apparently, other foundries working at 45 nm level
have had to do the same.

A potential advantage one sees is the considerable improvement in matching and 1/f noise, if
the oxide growth is so well controlled. Does anyone know about these details or have any comments?
One of course does not expect the lateral dimensions to be as well controlled as the vertical (matching),
but 1/f surely should get better.

Of course, the above improvements do not make analog design at 45 nm much easier.

Vivek

Title: Re: single layer oxide deposition process
Post by krishnap on Nov 28^th, 2007, 3:12am

gate leakage is more in this case, because of the thinner gate oxide.

Title: Re: single layer oxide deposition process
Post by Geoffrey_Coram on Nov 28^th, 2007, 8:01am

krishnap wrote on Nov 28^th, 2007, 3:12am:

gate leakage is more in this case, because of the thinner gate oxide.

Isn't it that same article (or maybe another one, referenced in the one cited above) that they talk about new high-k oxides (not SiO2) that reduce the gate leakage?

Title: Re: single layer oxide deposition process
Post by ACWWong on Nov 28^th, 2007, 3:24pm

Geoffrey_Coram wrote on Nov 28^th, 2007, 8:01am:

Isn't it that same article (or maybe another one, referenced in the one cited above) that they talk about new high-k oxides (not SiO2) that reduce the gate leakage?

yes, thats what i read as well... i think the point of the article is to say that using hi-k dielectric for the gate insulation allows a physically thicker gate (and so less gate leakage) but maintain the electrical field as if it was very thin SiO2... i.e. at 45nm technologies and beyond it'll probably be metal gate, hi-k dielectric devices rather than the poly gate with very thin SiO2 leaky devices we have now... but i agree it would be nice to get a hold of some analog device models/characteristics to see the performance etc.

Title: Re: single layer oxide deposition process
Post by vivkr on Nov 28^th, 2007, 11:00pm

Hi everyone,

My question was not about leakage at all. We all know that thinner gate oxides (newer processes) typically
have higher leakage. This one has high-K and so the leakage is probably a bit reduced.

The main question I had was about 1/f noise and matching, things which are not specified in the article. Since the 45 nm technology (not just Intel's but also from other vendors) uses a different, more precise method of oxide deposition, there should be much better oxide control and so lower 1/f noise.

Matching should also improve in principle. Usually, it anyway does as one goes to finer and finer features, but here, there should a significant jump due to change in processing method.

Has anyone worked in any 45 nm process? Perhaps, they can provide some insight into the performance improvement in terms of 1/f and matching when compared to say 65 nm, or 90 nm.

Regards
Vivek

Title: Re: single layer oxide deposition process
Post by Geoffrey_Coram on Nov 29^th, 2007, 6:36am

Indeed, Krishnap got us sidetracked. But I don't have any experience I can share about 45nm and 1/f.

Title: Re: single layer oxide deposition process
Post by Berti on Nov 29^th, 2007, 10:20pm

Hello,

I don't have any experience, too. ...but I think the main problem with high-k dielectrics and metal gates is
that the processing is difficult since the lattice structer doesn't match silicon as good as SiO2 does.
Therefore, even with better process control, flicker noise and matching might not become better because of
more interface defects.

But however, I am not a physician.
Regards