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Design >> Mixed-Signal Design >> Phase Noise/ Jitter for PLL
https://designers-guide.org/forum/YaBB.pl?num=1196126627

Message started by asako on Nov 26^th, 2007, 5:23pm

Title: Phase Noise/ Jitter for PLL
Post by asako on Nov 26^th, 2007, 5:23pm

I set up a PLL with verilogA function blocks as described in Mr. Kundert report.
Now, PLL converges, but when I plot phase noise using the Matlab code from the report,
I saw a huge degradation compared to single VCO or clock simulation result.

Then, I notice that the Mr. Kundert report also shows same effect; VCO's phase noise is -110dB/Hz@100KHz from Spectre RF, however, phase noise calculated in Matlab code is around -40dB/Hz.
How should I comprehend this ? Is there any good way to set convergence/accuracy setting ?