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Simulators >> Circuit Simulators >> subckt
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Message started by orion on Nov 26^th, 2007, 7:22pm

Title: subckt
Post by orion on Nov 26^th, 2007, 7:22pm

I am trying to run a spectre simulation using a subckt which is defined in a file.
for simplicity, I will define a simple test file:

in a file ckt.scs, the following lines are included which I load into the ADE Setup->Model Library Setup

subckt testcell (1 2 99)
parameters a=5 b=a*6+4
c0 ( 2 99) capacitor c=a
l0 ( 1 2) inductor l=b
ends testcell

the top circuit schematic is simple so the netlist looks like

simulator lang=spectre
global 0
include "/home/user/ckt.scs"

// Cell name: testcell
// View name: schematic
subckt testcell A B SUB
ends testcell
// End of subcircuit definition

// Cell name: ttest
// View name: schematic
I0 (net1 0 0) testcell
V0 (net1 0) vsource mag=1 type=dc
simulatorOptions options .....
dc0p dc write......
...

The schematic for testcell just has ports drawn since the circuit is defined in the subckt file ckt.scs

The error message that I receive in the simulator output when running is

Error found by spectre during circuit read-in.
"input.scs" 14: 'testcell' is being redefined

How can I get this to work if I want to include the subckt definition in the file ckt.scs and without manually changing the input.scs file?

Title: Re: subckt
Post by achim.graupner on Nov 26^th, 2007, 9:52pm

Hi orion,

the problem of you spectre netlist is the re-definition of the subckt testcell. In order to avoid the netlister to netlist the empty schematic you may try just to delete that cellview. Maybe you have to add "symbol" as stopping view in the view switch list.

HTH,
Achim

Title: Re: subckt
Post by orion on Nov 27^th, 2007, 11:30am

Hello Achim,
Just deleting the schematic view didn't work and the stop view list settings in the environment options would effect the
entire top level schematic. In using this block "testcell", it would be connected with other symbols blocks with schematics in them.

-orion

Title: Re: subckt
Post by achim.graupner on Nov 28^th, 2007, 12:13am

Hello Orion

what about using a VerilogA description instead of a subckt? IN VerilogA you can use structural description as well as parameters,

If you need, I could provide you a code example.

Achim

Title: Re: subckt
Post by orion on Nov 28^th, 2007, 11:40am

Achim,
sounds like a solution!
Yes, can u provide me w/an example.
thanks!

-orion