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Design >> Mixed-Signal Design >> PLL non-ideality
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Message started by aaron_do on Dec 10^th, 2007, 7:31pm

Title: PLL non-ideality
Post by aaron_do on Dec 10^th, 2007, 7:31pm

Hi all,

I have a PLL which I am trying to simulate. The PLL has no problem locking after around 50 us with less than 1 mV variation in the control voltage. After 60 us, I introduced a change in the tank capacitance on the order fF. The PLL doesn't seem to have gone out of lock completely since the DC value of the control voltage remains the same. Unfortunately, there is a 2 mV periodic signal of 1 MHz on the control voltage. I'm not sure where this is coming from. Does anybody know about this?

thanks,
Aaron

Title: Re: PLL non-ideality
Post by Berti on Dec 10^th, 2007, 11:40pm

Hi Aaron,

What is the reference clock frequency?

Regards

Title: Re: PLL non-ideality
Post by aaron_do on Dec 11^th, 2007, 3:33am

Hi,

the reference frequency is also 1 MHz. I expected the PLL to unlock and then slowly go back into lock...

Aaron

BTW the VCO frequency is about 2.4 GHz

Title: Re: PLL non-ideality
Post by vivkr on Dec 11^th, 2007, 7:31am

Hi Aaron,

Berti's question is the answer in itself. You are seeing ripple on the control voltage at the same frequency with
which you are updating your chargepump. Why is this unexpected for you?

Regards
Vivek

Title: Re: PLL non-ideality
Post by aaron_do on Dec 11^th, 2007, 5:43pm

Hi Vivek,

actually i'm not too familiar with PLL design, but the thing is the 1 MHz ripple is not there (at least not nearly as large) when the PLL locks for the first time. Only after I introduce the change in the tank capacitance. Also, the ripple does not seem to go away after an additional 40 us despite the fact that the PLL only took 50 us to lock in the first place.

cheers,
Aaron

Title: Re: PLL non-ideality
Post by vivkr on Dec 12^th, 2007, 10:59pm

Hi Aaron,

It has been quite a while since I did PLLs, but from what I recall, the ripple at reference frequency is typically determined
by the loop parameters of the PLL (the chargepump current and the passive elements, C1, C2 and R in the standard scheme).
You mention that you changed the filter cap by just a few fF. This should normally not cause a dramatic change.
I imagine that you have too little of C2 (the cap directly tied between the control voltage node and ground). All this
assuming that you are using one of the conventional chargepump PLL schemes.

Perhaps, you could post a snap of your filter and a couple of snaps of the ripple, and perhaps someone could help then.

Regards
Vivek

Title: Re: PLL non-ideality
Post by aaron_do on Dec 13^th, 2007, 7:24pm

Hi all,

here's a plot of the control voltage of the PLL, and the loop filter. The last cap on the loop filter was increased from 4p to 5p to see if there would be any change. Also, in this simulation, the PLL was simulated for 50 us before applying the change in tank capacitance of the VCO, so the control voltage is not quite as settled as it would be after 60 us. Any thoughts on why I am getting this ripple are welcome. Plots of the divider output and the reference frequency suggest that the PLL has not left the locked condition.

thanks,
Aaron

Title: Re: PLL non-ideality
Post by jeffyan on Dec 13^th, 2007, 9:34pm

aaron_do wrote on Dec 13^th, 2007, 7:24pm:

thanks,
Aaron

hi
i think it maybe caused by the fact that the freq of LC oscillaor changed too much, so that the loop need to re-settle.
and i think the loop will lock again after some time, is the large ringing lasting ?
good luck
jeff

Title: Re: PLL non-ideality
Post by aaron_do on Dec 13^th, 2007, 11:58pm

Hi Jeff,

thanks for the reply. The ringing is persisting and doesn't seem to be reducing (after an additional 40us...the initial lock time was only 50us). Furthermore, the PLL appears to be locked. The divider output is in phase with the reference clock.

Title: Re: PLL non-ideality
Post by Frank Wiedmann on Dec 14^th, 2007, 12:28am

You might want to try different initial conditions for your original circuit (with 4 pF). Perhaps the good settling was just by chance. Another thing you could try is simulating your modified circuit (with 5 pF) with various initial conditions (but without changing the value during the simulation). You could also try some other capacitance values and see if you can find a pattern.

Title: Re: PLL non-ideality
Post by aaron_do on Dec 14^th, 2007, 12:32am

thanks,

I also have a feeling the good settling may have been by chance. Only thing is it takes about 15 hrs to simulate the PLL so its difficult to play with the values and find out what's wrong...

Aaron

Title: Re: PLL non-ideality
Post by Frank Wiedmann on Dec 14^th, 2007, 1:28am

You might want to try using phase domain models to speed up simulation. See for example the pllLib from Cadence. The documentation is in Appendix G of the SpectreRF User Guide (http://sourcelink.cadence.com/docs/files/Release_Info/Docs/spectreRF/spectreRF6.1/appG.html).

Title: Re: PLL non-ideality
Post by vivkr on Dec 14^th, 2007, 2:37am

Dear Aaron,

I think Frank's suggestion is a good one. It is better to replace the various blocks with their equivalent phase-domain
models. This allows a much faster simulation.

Looking at your loop filter, I can see that it has 3 poles and a zero. This adds to the pole inherent in the VCO,
and the delay due to the divider.

Your ringing might also be owing to insuffcient damping in the loop. Perhaps you need to check the damping and
stability margins first. The phase domain model is a good starting point.

Regards
Vivek

Title: Re: PLL non-ideality
Post by Eugene on Dec 14^th, 2007, 8:23am

I agree that a phase domain model check is a good idea. It would allow you to rule out small signal instability.

I also think it is interesting that the larger oscillation starts with a sharp spike. How detailed is your model? Does it include various modes of operation, like precharging the loop filter? Is it possible that the spike occurs because the PLL enters an unexpected mode of operation?

Title: Re: PLL non-ideality
Post by aaron_do on Dec 14^th, 2007, 6:04pm

Hi all,

thanks for all the advice. I'll look into the phase domain model. Also the spike is a bit weird, so i guess i better investigate. I'm using detailed device models (Bsim3) and each block is designed down to the individual transistor sizes (it isn't in any standard library). In fact the change in capacitance i introduced is supposed to take place over a period of 1 us...

Anyway thanks for the help. I'll probably have to wait until after my holiday to do anything further.

happy holidays,
Aaron

Title: Re: PLL non-ideality
Post by jeffyan on Dec 15^th, 2007, 12:06am

aaron_do wrote on Dec 14^th, 2007, 6:04pm:

HI
i calculated the third and fourth pole's position introduced by your LPF, it seems that they are very close, one is about 291KHz and the other is 272KHz, right? what is your phase margin of the Loop.
have a check.
good luck
jeff

Title: Re: PLL non-ideality
Post by aaron_do on Dec 15^th, 2007, 3:07am

Hi Jeff,

thanks. Actually I didn't design the PLL and i don't know how either. Also, the guy who did has gone on holiday. If it's simple could you tell me how to check? From the sound of it it seems like i would need the phase domain model...

thanks,
Aaron

Title: Re: PLL non-ideality
Post by jeffyan on Dec 15^th, 2007, 11:54pm

aaron_do wrote on Dec 15^th, 2007, 3:07am:

hi,
it is hard to tell you how. but i can send you some papers about how to check the PLL loop stability in phase domain.
so could you tell me your mail address.
jeff

Title: Re: PLL non-ideality
Post by aaron_do on Dec 16^th, 2007, 3:55am

Hi Jeff,

thanks for the help. I managed to dig up some documents and i'll try it out as soon as possible.

thanks,
Aaron

Title: Re: PLL non-ideality
Post by vivkr on Dec 16^th, 2007, 11:11pm

Hi Aaron,

You could also get a useful approximation if you just treat phase as it were a voltage and make a simple model
which will simulate quite fast. This will allow you do to the stability analysis very easily.

You can look up the chapter of PLLs in Razavi's textbook for an idea. Your PLL has a PFD+chargepump, a loop filter,
the VCO and the divider.

The loop filter stays as it is. The VCO can be replaced by an integration with TF = Kvco/s. The Kvco is the
voltage-frequency conversion gain. You can find this by doing a set of simulations where you vary the control
voltage and see the output frequency. The (1/s) comes because phase is the integral of frequency.

The PFD in this domain is just a subtractor, while the chargepump is a current source with value = the pullup/pulldown currents
in your chargepump.

The divider needs to be replaced with a corresponding phase delay. With this, you can do your analysis. As Jeff already pointed
out, you have 2 very close poles in the filter.

Good Luck and be careful with factors of (2*pi) while setting up various parameters.

Vivek

Title: Re: PLL non-ideality
Post by wyyll on Dec 19^th, 2007, 10:52am

Hi Aaron,

If you look at the control voltage waveform after you add the capacitance to the LC tank, it suggests
that the PLL is locking, in response to a change in the trajectory of the tank. Consider that the period and
amplitude of the ringing changes with each successive cycle.

To see in your simulation if the loop has settled, plot out the voltage on the big damping capacitor. C11, in your
posted schematic. Has this voltage finished settling?

Having said this, I would again encourage you to get a phase domain model of some sort up and running,
as other before me have said.

I hope this helps.

Will