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Design Languages >> Verilog-AMS >> How to build D-Latch in verilogA without hidden st
https://designers-guide.org/forum/YaBB.pl?num=1197900394

Message started by AlexT on Dec 17^th, 2007, 6:06am

Title: How to build D-Latch in verilogA without hidden st
Post by AlexT on Dec 17^th, 2007, 6:06am

Hello Guys,
I have to build d-latch in verilogA without hidden states.
If anybody has advice, I will appreciate it very much.

Thanks a lot.
Alex.

Title: Re: How to build D-Latch in verilogA without hidde
Post by Ken Kundert on Dec 17^th, 2007, 9:18am

See RF Models at http://www.designers-guide.org/VerilogAMS/.

-Ken

Title: Re: How to build D-Latch in verilogA without hidde
Post by seefree on Dec 17^th, 2007, 2:01pm

You can define a flag signal when D and clk cross zero, and then, write the function of D-latch.