The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> op-amps, bias, and integration circuits
https://designers-guide.org/forum/YaBB.pl?num=1198002290

Message started by keystoneclimber on Dec 18^th, 2007, 10:24am

Title: op-amps, bias, and integration circuits
Post by keystoneclimber on Dec 18^th, 2007, 10:24am

Hello all,

I have a signal, of which the integral represents a process variable. (Fig. 1 of references.pdf) I designed a gated integrator (Fig. 2) to isolate the usable portion of the signal. I then sample this output with an ADC and scale appropriately. This works well, however the input signal can be bi-directional (Fig. 3) and the circuit doesn't support this. My first thought was to simply make everything bipolar. As it turns out though, my task of selecting an appropriate and reasonably priced ADC is much simpler if the output remains unipolar. My next thought was to apply both a DC offset to the input signal and an appropriate bias to the integrator. The idea was to get an output similar to the simulated signal in Fig. 4. I'm not sure if this is even possible. Typical non-gated integrators produce a triangle wave output from a square wave input. The gated variety produce a sawtooth wave. Here in lies the problem with my concept. Resetting the gate on the integrator sends the output to the bias point. I've yet to be able to figure out a way to send the output below the bias point.

The positive and negative signals are both important. So, this being the case I do care which side of zero it's on since it will indicate the polarity of the process variable. Think positive and negative pressure or flow. This is simply the way the transducer outputs the signal. I understand offsetting, biasing, and various circuit implementations to do so. I guess what I'm trying to figure out is if "negative integration" is possible. I did a simulation (simcircuit.png) and have yet to be able to get it to work. The maximum transducer input signal is +- 100mV. I offset this at 2Vdc and set my gain appropriately for a 2Vdc full scale output. The results are displayed in simoutput.png.

I can add a negative supply rail to that circuit but I'm not sure it will help because the lower limits of integration have been (in my experience) somehow limited by the bias. I used a negative rail in the simulation. The bias is set via the non-inverting input with a voltage divider, or by simply grounding if no DC bias is required. In the case of the first circuit, I use some feedback from the output for this which allows a linearity correction of sorts for distorted input signals. In the more recent circuit simulation, I've removed this and opted for the voltage divider configuration for simplicity while working out the bi-polar issues.

What I've found is two fold. First I've been unable to drive a signal more than about 0.5V below the bias point. Second, whenever the integrator is reset, the output is driven to the bias point. Both of these conditions can be seen in the simulation output on the red trace.

One idea I have is to duplicate the integrator with a unity gain inverting amplifier on the input. (simcircuit2.png) This achieves the desired result (simoutput2.png) but requires some extra parts. I can use a dual analog switch for the resets and a dual channel ADC to monitor both outputs simultaneously. The dual switch and triple (most likely quad) op amp packages don't add too much to the cost, but the dual ADC adds a significant amount. I was thinking that I could probably use a bi-polar ADC to do this using only a single part.

I was wondering if anyone can provide some insight as to alternative solutions?

http://home.comcast.net/~keystoneclimber/imagehost/references.pdf
http://home.comcast.net/~keystoneclimber/imagehost/simcircuit.png
http://home.comcast.net/~keystoneclimber/imagehost/simoutput.png
http://home.comcast.net/~keystoneclimber/imagehost/simcircuit2.png
http://home.comcast.net/~keystoneclimber/imagehost/simoutput2.png