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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> parameterize the dimension of variables https://designers-guide.org/forum/YaBB.pl?num=1198040383 Message started by Aigneryu on Dec 18th, 2007, 8:59pm |
Title: parameterize the dimension of variables Post by Aigneryu on Dec 18th, 2007, 8:59pm Hi, In verilog, we can parameterize thedimension of the bus, but I found it may not be allowed in verilog-a. Is this true? In verilog module abc(out, in); parameter bitnum=3; output [bitnum-1:0] out; input [bitnum-1:0] in; endmodule But I cannot do this in verilog-a. Is there any way to do this? I need to create an array of electrical signals while I wish to parameterize the dimension. Is there a way to achieve the following function? parameter integer dimension=3; electrical [dimension-1:0] node_voltage; |
Title: Re: parameterize the dimension of variables Post by Ken Kundert on Dec 19th, 2007, 10:15am This is not a limitation of Verilog-A, rather it is a limitation of the simulator. Are you using Spectre? Spectre has suffered from this problem since Verilog-A was introduced. I can sometimes work around the problem by using 'defines. -Ken |
Title: Re: parameterize the dimension of variables Post by Aigneryu on Dec 20th, 2007, 2:55pm Thanks Ken, That's right, I am using spectre in cadence. If I change to verilog-AMS, will it help? If I change to verilog-AMS, will it require more license compared to verilog-A (license for IUS may be required). Sincerely, |
Title: Re: parameterize the dimension of variables Post by Aigneryu on Dec 20th, 2007, 2:58pm Actually my question is how to make the following code more flexible in terms of parameter. This is a Gaussian filter which I want to use in analog simulation. `include "constants.vams" `include "disciplines.vams" module FIR4 (out, in, gnd, phi1, phi2); output out; electrical out; input in; electrical in; input gnd; electrical gnd; input phi1; electrical phi1; input phi2; electrical phi2; parameter real vth1 = 0.0 ; parameter real vth2 = 0.0 ; parameter real ctap = 10p ; parameter real roff = 1G ; //ohm parameter real ron = 0.1 ; //ohm parameter real osr = 16; parameter real fc_anti_alias = 4M; electrical [0:32] vphi1, vphi2, vc1, vc2; electrical vsum1, vsum2; real rphi1, rphi2; real tap_coeff [0:32]; real c_anti_alias; genvar m, n, p; analog begin @(initial_step) begin // initial condition of switches rphi1=roff; rphi2=ron; // set cap for anti alias filter c_anti_alias=1/(2*3.14159265358979*fc_anti_alias*100); // load tap coefficients tap_coeff [0] = 0.126951 ; tap_coeff [1] = 0.157485 ; tap_coeff [2] = 0.192665 ; tap_coeff [3] = 0.232450 ; tap_coeff [4] = 0.276577 ; tap_coeff [5] = 0.324536 ; tap_coeff [6] = 0.375553 ; tap_coeff [7] = 0.428589 ; tap_coeff [8] = 0.482361 ; tap_coeff [9] = 0.535382 ; tap_coeff [10] = 0.586026 ; tap_coeff [11] = 0.632602 ; tap_coeff [12] = 0.673451 ; tap_coeff [13] = 0.707037 ; tap_coeff [14] = 0.732048 ; tap_coeff [15] = 0.747477 ; tap_coeff [16] = 0.752692 ; tap_coeff [17] = 0.747477 ; tap_coeff [18] = 0.732048 ; tap_coeff [19] = 0.707037 ; tap_coeff [20] = 0.673451 ; tap_coeff [21] = 0.632602 ; tap_coeff [22] = 0.586026 ; tap_coeff [23] = 0.535382 ; tap_coeff [24] = 0.482361 ; tap_coeff [25] = 0.428589 ; tap_coeff [26] = 0.375553 ; tap_coeff [27] = 0.324536 ; tap_coeff [28] = 0.276577 ; tap_coeff [29] = 0.232450 ; tap_coeff [30] = 0.192665 ; tap_coeff [31] = 0.157485 ; tap_coeff [32] = 0.126951 ; end rphi1 = ((V(phi1) > vth1)? ron:roff); rphi2 = ((V(phi2) > vth2)? ron:roff); for (m=0; m<=32; m=m+1) begin //sampling I(vphi1[m], vc1[m]) <+ V(vphi1[m], vc1[m])/rphi1; I(vphi2[m], vc2[m]) <+ V(vphi2[m], vc2[m])/rphi2; //integration V(vc1[m], gnd) <+ idt(I(vc1[m], gnd)/ctap, 0); V(vc2[m], gnd) <+ idt(I(vc2[m], gnd)/ctap, 0); //following V(vphi2[m])<+V(vc1[m]); //filtering V(vsum1)<+tap_coeff[m]*V(vc2[m])/osr; end V(vphi1[0])<+V(in); for (n=1; n<=32; n=n+1) begin V(vphi1[n])<+V(vc2[n-1]); end I(vsum1, vsum2) <+ V(vsum1, vsum2)/100; V(vsum2, gnd) <+ idt(I(vsum2, gnd)/c_anti_alias, 0); V(out, gnd) <+ V(vsum2, gnd); end endmodule |
Title: Re: parameterize the dimension of variables Post by Ken Kundert on Dec 20th, 2007, 10:36pm Seems like a very expensive approach. Why don't you just use the z-domain filter functions? -Ken |
Title: Re: parameterize the dimension of variables Post by Aigneryu on Dec 21st, 2007, 1:00pm The reason I use this is because for some reason I need to play with the dual phase clocks. And I will also need to make a smooth transition for the switches in order to pass the small signal from the clock ports. |
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