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Simulators >> Circuit Simulators >> Passing parameters hierarchically to verilog cell
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Message started by rajdeep on Dec 24^th, 2007, 4:33am

Title: Passing parameters hierarchically to verilog cell
Post by rajdeep on Dec 24^th, 2007, 4:33am

Hi all,

Does anyone know how to pass parameter values hierarchically into a verilog cell??

pPar seems to be useful for spectre/VerilogA types of views. It's not working for
verilog modules.

Rajdeep

Title: Re: Passing parameters hierarchically to verilog c
Post by rajdeep on Dec 26^th, 2007, 3:00am

I forgot to mention. I'm using spectreVerilog and not AMS simulator.
Is it at all possible to do using spectreVerilog?