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Modeling >> Semiconductor Devices >> Nfet in Nwell capacitance?
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Message started by joel on Dec 28^th, 2007, 2:20pm

Title: Nfet in Nwell capacitance?
Post by joel on Dec 28^th, 2007, 2:20pm

I'm looking at a design that uses Nfet in Nwell to implement a single-terminal capacitor.
The foundry library does not include a model for this structure. How should I expect
the gate-capacitance to behave? Will it be significantly different from a native Nfet
(for which I have a model) or a standard Nfet whose Vth is hand-edited to zero?

One more question. Supposing I raise the voltage of the structure's nwell to Vdd
rather than its normal Vss tie. What happens to the gate capacitance in this configuration?

Thanks in advance for sharing your knowledge!

Title: Re: Nfet in Nwell capacitance?
Post by Terence on Jan 3^rd, 2008, 2:57am

How should I expect the gate-capacitance to behave?
==> the capacitance will be similar to Cox once you operate the nMOS in accumulation mode.

Will it be significantly different from a native Nfet (for which I have a model) or a standard Nfet whose Vth is hand-edited to zero?
==> I suggest to check foundry's document.

One more question. Supposing I raise the voltage of the structure's nwell to Vdd rather than its normal Vss tie. What happens to the gate capacitance in this configuration?
==> that will make the nMOS to operate at accumulation mode once you tie the gate to Vss. The capacitance will be close to Cox.