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Design >> Mixed-Signal Design >> PLL Layout
https://designers-guide.org/forum/YaBB.pl?num=1199083269

Message started by nanrma on Dec 30^th, 2007, 10:41pm

Title: PLL Layout
Post by nanrma on Dec 30^th, 2007, 10:41pm

SOC has PLL ,transmitter,receiver and some digital blocks. The placement is shown in the attached document.
A PLL (working as a freq synthesizer) gives clock to T1-4(which are blocks of transmitter) and R1-4 (which are blocks of receiver). At the receiver end we are getting a problem –bit errors are coming b/w R1,R2,R3,R4 i.e some delay is happening and coz of tht noise n jitter is happening post fab.What can be the possible solutions for this problem….is adding buffers between the paths a solution? Or can anyone suggest some possible solutions from layout point of view….

Title: Re: PLL Layout
Post by ywguo on Jan 2^nd, 2008, 7:18pm

Hi Nanrma,

I am not clear what the problem is. BTW, what does b/w mean?

Yawei

Title: Re: PLL Layout
Post by nanrma on Jan 2^nd, 2008, 9:09pm

Hi

b/w means between.
The problem is that we have a PLL on a chip which also has a transmitter and receiver(many sub blocks inside Transmitter n receiver:T1-4,R1-4)
This PLL gives clock to the Tx and Rx. On Silicon, we are facing problem at the receiver end: noise and jitter. We have observed that there is a problem with the clock that is coming from PLL to Rx. The clock has a skew at the receiver end. Different blocks of receiver are getting clock with some skew and hence we are getting bit errors. I am looking for a solution to this problem from both layout and design angle.

Title: Re: PLL Layout
Post by ywguo on Jan 2^nd, 2008, 10:58pm

Hi Nanrma,

What is the application? HDMI? It looks there should be two PLLs, one of which is for transmitter and the other of which is for receiver. Now that only one PLL feeds the clock to T1-4 and R1-4, is the clock synchronized with the input data to the receiver?

BTW, would you please describe how the bit error is measured?

Yawei

Title: Re: PLL Layout
Post by joel on Jan 29^th, 2008, 12:50pm

Adding buffers will increase jitter due to power-supply noise injection. But
you might be able to deal with your skew problem by path matching (e.g
identical buffer #, size, load) on each path. Lots of SerDes use a single pll,
but put local phase-interpolators on the clock-path or deskewing-buffers on
the data-path. I hope I'm understanding your question correctly, and not suggesting
the obvious!

Title: Re: PLL Layout
Post by loose-electron on Feb 1^st, 2008, 5:08pm

As a general rule, if youhave an RF receiver on a chip, anything that goes out to the leadframe of the package/chip is going to couple right into the front end of the LNA in the receiver.

Do the math, in some cases you need over 100db of isolation, and thats just not going to happen.

Jerry