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Design Languages >> VHDL-AMS >> sample and hold
https://designers-guide.org/forum/YaBB.pl?num=1199630127

Message started by safwatonline on Jan 6^th, 2008, 6:35am

Title: sample and hold
Post by safwatonline on Jan 6^th, 2008, 6:35am

i am new to VHDL-AMS and i am trying to model a sample and hold block in time domain.
i made this code but it aint working any hints please !

Quote:

LIBRARY IEEE_PROPOSED;
USE IEEE_PROPOSED.ELECTRICAL_SYSTEMS.ALL;
library ieee;
use ieee.math_real.all;
use IEEE.std_logic_1164.all;
ENTITY tro_sh IS
PORT
(
terminal vin, vout, vss: electrical;
signal clk : in std_logic
);
END tro_sh;

ARCHITECTURE arch OF tro_sh IS
quantity vi across ii through vin to vss;
quantity vo across vout to vss;
signal samp : real :=0.0;
BEGIN
sampling:process
begin
wait until (clk'event and clk= '1');
samp <= vi;
end process sampling;
vo == samp;
break on clk;
END arch;

Title: Re: sample and hold
Post by mikej on Jan 8^th, 2008, 11:38am

Try using the zero-order hold ('zoh) attribute, which is essentially a sample-hold function. The attribute can be used with any quantity and has the following syntax:

Q'zoh(T,initial_delay)

where "Q" is the quantity to be sampled, "T" is the sampling interval, and "initial_delay" is the delay before the first sample is taken. The result of the command is a quantity of the same type as Q. Time T must be a static expression of type real and greater than 0.0. Initial_delay must be a static expression of type real and non-negative. If you don't need a delay before the first sample is taken, you can use the following syntax:

Q'zoh(T)

Title: Re: sample and hold
Post by safwatonline on Jan 9^th, 2008, 12:18pm

Thanks for ur answer, but i want the model to sample the analog input quantity when a clock signal coming from another terminal arrives i.e. i want to sample on the edge of a signal coming from a terminal and not at fixed period.

Title: Re: sample and hold
Post by Sameer Kher on Jan 10^th, 2008, 1:48pm

The code looks ok for what you are trying to do. Perhaps the problem is elsewhere? What results do you get?

BTW, the electrical systems package has been standardized for a while now (no longer proposed). You should use
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
...

Hope this helps.
Thanks,
Sameer

Title: Re: sample and hold
Post by safwatonline on Jan 11^th, 2008, 6:19am

Sameer Kher wrote on Jan 10^th, 2008, 1:48pm:

the output is not following the input , it is zero and doesnt change either with the clock or input

Title: Re: sample and hold
Post by didac on Jan 11^th, 2008, 6:59am

Hi,
Haven't work with behavioral description for a while but I think that you should include the clk signal inside the sensible list of process(if not included I think that it will never activate):
process(clk) begin
end process;
Hope it helps,

Title: Re: sample and hold
Post by Sameer Kher on Jan 11^th, 2008, 1:28pm

didac, all,

With VHDL-AMS, you either specify the process sensitivity list or have appropriate wait statements to ensure that your process is correctly triggered. So the code should work.

Perhaps you can verify that the problem is indeed only in the S&H model by using it by itself (assuming you are using it in a system). It may be an implementation bug in the software.

Good luck,
Sameer

Title: Re: sample and hold
Post by safwatonline on Jan 12^th, 2008, 9:11am

Sameer Kher wrote on Jan 11^th, 2008, 1:28pm:

yep, it is not working by itself,
maybe someone can share a working sample and hold code
thanks